AD7356BRUZ Analog Devices Inc, AD7356BRUZ Datasheet - Page 16

• Manufacturer Part Number: AD7356BRUZ
• Description: 12-Bit Dual Diff Simult 5 MSPS ADC I.C.
• Manufacturer: Analog Devices Inc

Specifications of AD7356BRUZ

• Design Resources: DC-Coupled, Single-Ended-to-Differential Conversion Using AD8138 and AD7356 (CN0041)
• Number Of Bits: 12
• Sampling Rate (per Second): 3M
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 59mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP (0.173", 4.40mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7356
FULL POWER-DOWN MODE
Full power-down mode is intended for use in applications
where throughput rates slower than those in partial power-
down mode are required because power-up from a full power-
down takes substantially longer than that from a partial power-
down. This mode is more suited to applications in which a
series of conversions performed at a relatively high throughput
rate are followed by a long period of inactivity and, thus, power-
down. When the AD7356 is in full power-down mode, all
analog circuitry is powered down including the on-chip
reference and reference buffers. Full power-down mode is
entered in a similar way as partial power-down mode, except
that the timing sequence shown in Figure 25 must be executed
twice. The conversion process must be interrupted in a similar
fashion by bringing CS high anywhere after the second falling
edge of SCLK and before the 10
device enters partial power-down mode at this point.
SDATA
SDATA
SDATA
SDATA
SDATA
SDATA
SCLK
SCLK
SCLK
CS
CS
CS
A
B
A
B
A
B
THE PART BEGINS
TO POWER UP.
1
1
1
2
th
INVALID DATA
THE PART BEGINS
TO POWER UP.
falling edge of SCLK. The
PARTIAL POWER-DOWN MODE.
THE PART ENTERS
INVALID DATA
INVALID DATA
t
t
POWER-UP1
POWER-UP2
Figure 26. Exiting Partial Power-Down Mode
Figure 27. Entering Full Power-Down Mode
Figure 28. Exiting Full Power-Down Mode
10
10
THREE-STATE
10
Rev. 0 | Page 16 of 20
14
14
THE PART BEGINS
14
TO POWER UP.
To reach full power-down, the next conversion cycle must be
interrupted in the same way, as shown in Figure 27. When CS is
brought high in this window of SCLKs, the part fully powers
down.
Note that it is not necessary to complete the 14 or 16 SCLKs
once CS has been brought high to enter a power-down mode.
To exit full power-down mode and power-up the AD7356,
perform a dummy conversion, similar to powering up from
partial power-down. On the falling edge of CS , the device begins
to power up as long as CS is held low until after the falling edge
of the 10
before a conversion can be initiated, as shown in
1
th
2
SCLK. The required power-up time must elapse
INVALID DATA
1
1
THE PART IS FULLY POWERED UP;
SEE THE POWER-UP TIMES SECTION.
FULL POWER-DOWN MODE.
THE PART IS FULLY POWERED UP;
SEE THE POWER-UP TIMES SECTION.
THE PART ENTERS
VALID DATA
VALID DATA
10
THREE-STATE
14
14
14
Figure 28
.