AD7650ACPZRL Analog Devices Inc, AD7650ACPZRL Datasheet - Page 3

• Manufacturer Part Number: AD7650ACPZRL
• Description: 1MSPS, 16-Bit ADC Int Ref, 2.5LSB
• Manufacturer: Analog Devices Inc

Specifications of AD7650ACPZRL

• Number Of Bits: 16
• Sampling Rate (per Second): 570k
• Data Interface: Serial, Parallel
• Number Of Converters: 1
• Power Dissipation (max): 77mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VFQFN, CSP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7650CBZ - BOARD EVALUATION FOR AD7650
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TIMING SPECIFICATIONS
Parameter
REFER TO FIGURES 8 AND 9
REFER TO FIGURES 10, 11 AND 12
REFER TO FIGURES 13 AND 14
Parameter
POWER SUPPLIES (continued)
TEMPERATURE RANGE
NOTES
1
2
3
4
5
6
7
8
9
Specifications subject to change without notice.
LSB means Least Significant Bit. With the 0 V to 2.5 V input range, one LSB is 38.15 µV.
See Definition of Specifications section. These specifications do not include the error contribution from the external reference.
Tested in warp mode.
All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale unless otherwise specified.
In warp mode.
Tested in parallel reading mode.
In impulse mode.
With all digital inputs forced to OVDD or OGND respectively.
Contact factory for extended temperature range.
Convert Pulsewidth
Time Between Conversions
CNVST LOW to BUSY HIGH Delay
BUSY HIGH All Modes Except in
Aperture Delay
End of Conversion to BUSY LOW Delay
Conversion Time
Acquisition Time
RESET Pulsewidth
(Parallel Interface Modes)
CNVST LOW to DATA Valid Delay
DATA Valid to BUSY LOW Delay
Bus Access Request to DATA Valid
Bus Relinquish Time
(Master Serial Interface Modes)
CS LOW to SYNC Valid Delay
CS LOW to Internal SCLK Valid Delay
CS LOW to SDOUT Delay
CNVST LOW to SYNC Delay
SYNC Asserted to SCLK First Edge Delay
Internal SCLK Period
Internal SCLK HIGH (INVSCLK Low)
Internal SCLK LOW (INVSCLK Low)
SDOUT Valid Setup Time
SDOUT Valid Hold Time
Operating Current
Power Dissipation
Specified Performance
(Warp Mode/Normal Mode/Impulse Mode)
Master Serial Read After Convert Mode
(Warp Mode/Normal Mode/Impulse Mode)
(Warp Mode/Normal Mode/Impulse Mode)
(Warp Mode/Normal Mode/Impulse Mode)
(Warp Mode/Normal Mode/Impulse Mode)
AVDD
DVDD
OVDD
6
6
6
5
9
2
Condition
570 kSPS Throughput
570 kSPS Throughput
444 kSPS Throughput
100 SPS Throughput
In Power-Down Mode
T
MIN
(–40 C to +85 C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)
3
2
to T
3
MAX
7
5
7
8
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Min
–40
Min
5
1.75/2/2.25
10
250
10
45
5
4
40
30
9.5
4.5
3
Typ
15.5
4.2
100
77
21
Typ
2
25/275/525
Max
115
7
+85
Max
Note 1
30
1.5/1.75/2
1.5/1.75/2
1.5/1.75/2
40
15
10
10
10
75
AD7650
Unit
mA
mA
µA
mW
mW
µW
µW
°C
AD7650
Unit
ns
µs
ns
µs
ns
ns
µs
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns