AD7706BRUZ Analog Devices Inc, AD7706BRUZ Datasheet - Page 17

• Manufacturer Part Number: AD7706BRUZ
• Description: IC,Data Acquisition Signal Conditioner,3-CHANNEL,16-BIT,CMOS,TSSOP,16PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of AD7706BRUZ

• Number Of Bits: 16
• Sampling Rate (per Second): 500
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 1mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP (0.173", 4.40mm Width)
• Package: 16TSSOP
• Resolution: 16 Bit
• Sampling Rate: 0.5 KSPS
• Architecture: Delta-Sigma
• Number Of Adcs: 1
• Number Of Analog Inputs: 3
• Digital Interface Type: Serial (3-Wire, SPI, QSPI, Microwire)
• Input Type: Voltage
• Signal To Noise Ratio: 116 dB
• Polarity Of Input Voltage: Unipolar|Bipolar
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7706EBZ - BOARD EVALUATION FOR AD7706
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 11. Register Selection
RS2
0
0
0
0
1
1
1
1
Table 12. Channel Selection for AD7705
CH1
0
0
1
1
Table 13. Channel Selection for AD7706
CH1
0
0
1
1
SETUP REGISTER (RS2, RS1, RS0 = 0, 0, 1); POWER-ON/RESET STATUS: 01 HEXADECIMAL
The setup register is an 8-bit register from which data can be read or to which data can be written.
Table 14 outlines the bit designations for the setup register.
Table 14. Setup Register
MD1 (0)
Table 15. Setup Register Description
Register
MD1, MD0
G2 to G0
B/U
BUF
FSYNC
Description
ADC Mode Bits. These bits select the operational mode of the ADC as outlined in Table 16.
Gain Selection Bits. These bits select the gain setting for the on-chip PGA, as outlined in Table 17.
Bipolar/Unipolar Operation. A 0 in this bit selects bipolar operation; a 1 in this bit selects unipolar operation.
Buffer Control. With this bit at 0, the on-chip buffer on the analog input is shorted out. With the buffer shorted out, the current
flowing in the V
to handle higher source impedances.
Filter Synchronization. When this bit is high, the nodes of the digital filter, the filter control logic, the calibration control logic,
and the analog modulator are held in a reset state. When this bit goes low, the modulator and filter start to process data, and
a valid word is available in 3 × 1/output rate, that is, the settling time of the filter. This FSYNC bit does not affect the digital
interface and does not reset the DRDY output if it is low.
CH0
0
1
0
1
RS1
0
0
1
1
0
0
1
1
CH0
0
1
0
1
MD0 (0)
DD
AIN
AIN1
AIN2
COMMON
AIN3
RS0
0
1
0
1
0
1
0
1
line is reduced. When this bit is high, the on-chip buffer is in series with the analog input, allowing the input
AIN(+)
AIN1(+)
AIN2(+)
AIN1(−)
AIN1(−)
G2 (0)
Register
Communication register
Setup register
Clock register
Data register
Test register
No operation
Offset register
Gain register
G1 (0)
AIN1(−)
AIN2(−)
AIN1(−)
AIN2(−)
AIN(−)
COMMON
COMMON
COMMON
Reference
COMMON
Rev. C | Page 17 of 44
G0 (0)
Register Pair 0
Register Pair 1
Register Pair 0
Register Pair 2
Calibration Register Pair
Register Pair 0
Register Pair 1
Register Pair 2
Calibration Register Pair
Register Pair 0
B/U (0)
BUF (0)
Register Size
8 bits
8 bits
8 bits
16 bits
8 bits
24 bits
24 bits
AD7705/AD7706
FSYNC (1)