AD7715AR-3 Analog Devices Inc, AD7715AR-3 Datasheet - Page 30

• Manufacturer Part Number: AD7715AR-3
• Description: A/D Converter (A-D) IC
• Manufacturer: Analog Devices Inc

Specifications of AD7715AR-3

• No. Of Bits: 16 Bit
• Mounting Type: Surface Mount
• Features: 3V, 16?Bit Sigma?Delta ADC W/PGA
• No. Of Channels: 1
• Interface Type: Serial
• Package / Case: 16-SOIC
• Rohs Status: RoHS non-compliant
• Number Of Bits: 16
• Sampling Rate (per Second): 500
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 9.5mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• For Use With: EVAL-AD7715-3EBZ - BOARD EVALUATION FOR AD7715

AD7715
Figure 8 and Figure 9 show timing diagrams for interfacing to
the AD7715 with CS used to decode the part.
read operation from the AD7715’s output shift register, while
Figure 9
possible to read the same data twice from the output register
even though the
operation. Take care, however, to ensure that the read operations
have been completed before the next output update is about to
take place.
The AD7715 serial interface can operate in three-wire mode by
tying the CS input low. In this case, the SCLK, DIN and DOUT
lines are used to communicate with the AD7715 and the status
of DRDY can be obtained by interrogating the MSB of the com-
munications register. This scheme is suitable for interfacing to
microcontrollers. If CS is required as a decoding signal, it can
be generated from a port bit. For microcontroller interfaces, it is
recommended that the SCLK idles high between data transfers.
The AD7715 can also be operated with CS used as a frame
synchronization signal. This scheme is suitable for DSP
interfaces. In this case, the first bit (MSB) is effectively clocked
out by CS because CS would normally occur after the falling
edge of SCLK in DSPs. The SCLK can continue to run between
data transfers provided the timing numbers are obeyed.
shows a write operation to the input shift register. It is
DRDY line returns high after the first read
SCLK
DRDY
DOUT
SCLK
DIN
CS
CS
t
3
t
5
t
t
11
4
t
12
Figure 8
MSB
MSB
t
13
Figure 9. Write Cycle Timing Diagram
Figure 8. Read Cycle Timing Diagram
is for a
t
t
6
14
Rev. D | Page 30 of 40
t
t
15
7
The serial interface can be reset by exercising the RESET input
on the part. It can also be reset by writing a series of 1s on the
DIN input. If a Logic 1 is written to the AD7715 DIN line for
at least 32 serial clock cycles, the serial interface is reset. This
ensures that in three-wire systems that if the interface gets lost
either via a software error or by some glitch in the system, it can
be reset back into a known state. This state returns the interface
to where the AD7715 is expecting a write operation to its com-
munications register. This operation in itself does not reset the
contents of any registers, but because the interface was lost, the
information that was written to any of the registers is unknown
and it is advisable to set up all registers again.
Some microprocessor or microcontroller serial interfaces have
a single serial data line. In this case, it is possible to connect
the DOUT and DIN lines of the AD7715 together and connect
them to the single data line of the processor. A 10 kΩ pull-up
resistor should be used on this single data line. In this case, if
the interface gets lost, because the read and write operations
share the same line the procedure to reset it back to a known
state is somewhat different than described previously. It requires
a read operation of 24 serial clocks followed by a write operation
where a Logic 1 is written for at least 32 serial clock cycles to
ensure that the serial interface is back into a known state.
LSB
LSB
t
10
t
8
t
9
t
16