AD7890BNZ-2 Analog Devices Inc, AD7890BNZ-2 Datasheet - Page 15

• Manufacturer Part Number: AD7890BNZ-2
• Description: IC,Data Acquisition System,8-CHANNEL,12-BIT,DIP,24PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Type: Data Acquisition System (DAS)r

Specifications of AD7890BNZ-2

• Resolution (bits): 12 b
• Sampling Rate (per Second): 117k
• Data Interface: Serial
• Voltage Supply Source: Single Supply
• Voltage - Supply: 0 V ~ 2.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Through Hole
• Package / Case: 24-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

In the self-clocking mode, the AD7890 indicates when
conversion is complete by bringing the RFS line low and
initiating a serial data transfer. In the external clocking mode,
there is no indication of when conversion is complete. In many
applications, this is not a problem as the data can be read from
the part during conversion or after conversion. However,
applications that seek to achieve optimum performance from
the AD7890 has to ensure that the data read does not occur
during conversion or during 500 ns prior to the rising edge
of CONVST .
This can be achieved in either of two ways. The first is to ensure
in software that the read operation is not initiated until 5.9 μs
after the rising edge of CONVST . This is only possible if the
software knows when the CONVST command is issued. The
second scheme would be to use the CONVST signal as both the
conversion start signal and an interrupt signal. The simplest
way to do this is to generate a square wave signal for CONVST
with high and low times of 5.9 μs (see Figure 8). Conversion is
initiated on the rising edge of CONVST . The falling edge of
CONVST
SCLK
RFS
TFS
TRACK/HOLD GOES
CONVERSION IS
INITIATED AND
INTO HOLD
t
Figure 8. CONVST Used as Status Signal in External Clocking Mode
CONVERT
CONVERSION
ENDS 5.9µs
LATER
Rev. C | Page 15 of 28
MICROPROCESSOR
INT SERVICE
OR POLLING
ROUTINE
CONVST occurs 5.9 μs later and can be used as either an active
low or falling edge-triggered interrupt signal to tell the
processor to read the data from the AD7890. Provided the read
operation is completed 500 ns before the rising edge of
CONVST , the AD7890 operates to specification.
This scheme limits the throughput rate to 11.8 μs minimum.
However, depending upon the response time of the
microprocessor to the interrupt signal and the time taken by the
processor to read the data, this may be the fastest which the
system could have operated. In any case, the CONVST signal
does not have to have a 50:50 duty cycle. This can be tailored to
optimize the throughput rate of the part for a given system.
Alternatively, the CONVST signal can be used as a normal
narrow pulse width. The rising edge of CONVST can be used as
an active high or rising edge-triggered interrupt. A software
delay of 5.9 μs can then be implemented before data is read
from the part.
SERIAL READ
OPERATIONS
AND WRITE
OPERATIONS SHOULD
READ AND WRITE
EDGE OF CONVST
END 500ns PRIOR
TO NEXT RISING
500ns MIN
NEXT CONVST
RISING EDGE
AD7890