AD8251ARMZ-RL Analog Devices Inc, AD8251ARMZ-RL Datasheet - Page 17

• Manufacturer Part Number: AD8251ARMZ-RL
• Description: IC,Instrumentation Amplifier,SINGLE,TSSOP,10PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: iCMOS®r

Specifications of AD8251ARMZ-RL

• Amplifier Type: Instrumentation
• Number Of Circuits: 1
• Slew Rate: 30 V/µs
• -3db Bandwidth: 10MHz
• Current - Input Bias: 5nA
• Voltage - Input Offset: 70µV
• Current - Supply: 4.1mA
• Current - Output / Channel: 37mA
• Voltage - Supply, Single/dual (±): 10 V ~ 30 V, ±5 V ~ 15 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Output Type: -
• Gain Bandwidth Product: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 5. Truth Table Logic Levels for Transparent Gain Mode
WR
−V
−V
−V
−V
Latched Gain Mode
Some applications have multiple programmable devices such as
multiplexers or other programmable gain instrumentation
amplifiers on the same PCB. In such cases, devices can share a
data bus. The gain of the AD8251 can be set using WR as a latch,
allowing other devices to share A0 and A1.
schematic using this method, known as latched gain mode. The
AD8251 is in this mode when
low, typically 5 V and 0 V, respectively. The voltages on A0 and A1
are read on the downward edge of the WR signal as it transitions
from logic high to logic low. This latches in the logic levels on
A0 and A1, resulting in a gain change. See the truth table in
Table 6
NOTE:
1. ON THE DOWNWARD EDGE OF WR, AS IT TRANSITIONS
S
S
S
S
FROM LOGIC HIGH TO LOGIC LOW, THE VOLTAGES ON A0
AND A1 ARE READ AND LATCHED IN, RESULTING IN A
GAIN CHANGE. IN THIS EXAMPLE, THE GAIN SWITCHES TO G = 8.
–IN
for more information on these gain changes.
+IN
10μF
10μF
0.1µF
0.1µF
A1
Low
Low
High
High
Figure 53. Latched Gain Mode, G = 8
+15V
–15V
+
–
AD8251
DGND
WR
A1
WR is held at logic high or logic
A0
Low
High
Low
High
A0
REF
G = PREVIOUS
STATE
DGND
WR
A1
A0
A0, A1
WR
Figure 53
G = 8
Gain
1
2
4
8
+5V
0V
+5V
0V
+5V
0V
Figure 54. Timing Diagram for Latched Gain Mode
shows a
t
WR-HIGH
Rev. B | Page 17 of 24
t
SU
t
HD
t
WR-LOW
Table 6. Truth Table Logic Levels for Latched Gain Mode
WR
High to low
High to low
High to low
High to low
Low to low
Low to high
High to high
1
On power-up, the AD8251 defaults to a gain of 1 when in latched
gain mode. In contrast, if the AD8251 is configured in transparent
gain mode, it starts at the gain indicated by the voltage levels on
A0 and A1 at power-up.
Timing for Latched Gain Mode
In latched gain mode, logic levels at A0 and A1 must be held for
a minimum setup time, t
latches in the gain. Similarly, they must be held for a minimum
hold time of t
the gain is latched in correctly. After t
logic levels, but the gain does not change (until the next
downward edge of WR ). The minimum duration that WR can
be held high is t
can be held low is t
listed in
dominated by the settling time of the amplifier. A timing
diagram is shown in
When sharing a data bus with other devices, logic levels applied
to those devices can potentially feed through to the output of
the AD8251. Feedthrough can be minimized by decreasing the
edge rate of the logic signals. Furthermore, careful layout of the
PCB also reduces coupling between the digital and analog portions
of the board. Pull-up or pull-down resistors should be used to
provide a well-defined voltage at the A0 and A1 pins.
X = don’t care.
Table 2.
HD
WR
after the downward edge of WR to ensure that
The time required for a gain change is
-HIGH
WR
A1
Low
High
X
X
X
Low
High
Figure 54
1
1
1
-LOW
, and the minimum duration that WR
SU
. Digital timing specifications are
, before the downward edge of WR
A0
Low
High
Low
High
X
X
X
.
1
1
1
HD
Gain
Change to 1
Change to 2
Change to 4
Change to 8
No change
No change
No change
, A0 and A1 can change
AD8251