AD9211BCPZ-250 Analog Devices Inc, AD9211BCPZ-250 Datasheet
AD9211BCPZ-250
Specifications of AD9211BCPZ-250
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AD9211BCPZ-250 Summary of contents
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FEATURES SNR = 60.1 dBFS @ MHz @ 300 MSPS IN ENOB of 9 MHz @ 300 MSPS (−1.0 dBFS) IN SFDR = −80 dBc @ MHz ...
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AD9211 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 DC Specifications ......................................................................... 3 AC Specifications.......................................................................... 4 Digital Specifications ................................................................... 5 Switching ...
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SPECIFICATIONS DC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1 −40°C, T MIN Table 1. 1 Parameter Temp RESOLUTION ACCURACY No Missing Codes Full Offset Error 25°C Full Gain Error 25°C Full Differential Nonlinearity (DNL) 25°C Full ...
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AD9211 1 AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1 −40°C, T MIN Table 2. 2 Parameter SNR MHz MHz 170 MHz IN SINAD f = ...
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DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1 −40°C, T MIN Table 3. 1 Parameter Temp CLOCK INPUTS Logic Compliance Full Internal Common-Mode Bias Full Differential Input Voltage Full Input Voltage Range Full Input Common-Mode Range ...
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AD9211 SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1 −40°C, T MIN Table 4. Parameter (Conditions) Temp Maximum Conversion Rate Full Minimum Conversion Rate Full CLK+ Pulse Width High (t ) Full CH CLK+ Pulse Width ...
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TIMING DIAGRAMS N – 1 VIN CLK+ CLK– t CPD DCO+ DCO– Dx+ Dx– N – 1 VIN CLK+ CLK– t CPD DCO+ DCO– D0/D5+ D0/D5– D4/D9+ D4/D9– ...
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AD9211 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter ELECTRICAL AVDD to AGND DRVDD to DRGND AGND to DRGND AVDD to DRVDD D0+/D0− through D9+/D9− to DRGND DCO to DRGND OR to DGND CLK+ to AGND CLK− to AGND VIN+ to AGND ...
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PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Table 7. Single Data Rate Mode Pin Function Descriptions Pin No. Mnemonic 30 34 39, AVDD 24, 47 DRVDD 0 AGND 23, 48 ...
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AD9211 Pin No. Mnemonic 11 D5− 12 D5+ 13 D6− 14 D6+ 15 D7− 16 D7+ 17 D8− 18 D8+ 19 D9− 20 D9+ 21 OR− 22 OR+ 1 AGND and DRGND should be tied to a common quiet ground ...
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Table 8. Double Data Rate Mode Pin Function Descriptions Pin No. Mnemonic 30 34 39, AVDD 24, 47 DRVDD 0 AGND 23, 48 DRGND 35 VIN+ 36 VIN− ...
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AD9211 Pin No. Mnemonic 9 OR− 20, 51, 52 DNC 21 DNC/(OR−) 22 DNC/(OR+) 1 AGND and DRGND should be tied to a common quiet ground plane. Description D6 Complement Output Bit. (This pin is disabled ...
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TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 1.8 V, DRVDD = 1.8 V, rated sample rate, DCS enabled, T otherwise noted. 0 –20 –40 –60 –80 –100 –120 FREQUENCY (MHz) Figure 6. AD9211-200 64k Point Single-Tone FFT; 200 MSPS, ...
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AD9211 0.5 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5 0 256 512 OUTPUT CODE Figure 12. AD9211-200 DNL; 200 MSPS 0 –20 –40 –60 –80 –100 –120 0 31.25 62.50 FREQUENCY (MHz) Figure 13. AD9211-250 64k Point ...
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OUTPUT CODE Figure 18. AD9211-250 INL; 250 MSPS 0.5 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5 0 256 512 OUTPUT CODE Figure 19. ...
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AD9211 90 SFDR (dBFS SNR (dBFS SFDR (dB –90 –80 –70 –60 –50 –40 AMPLITUDE (dBFS) Figure 24. AD9211-300 SNR/SFDR vs. Input Amplitude; 300 MSPS, 170.3 MHz 0.25 0.20 0.15 0.10 ...
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SFDR (dBc SNR (dB 1.0 1.1 1.2 1.3 1.4 1.5 1.6 V (V) CM Figure 30. SNR/SFDR vs. Common-Mode Voltage; 300 MSPS, 70.3 MHz @ −1 dBFS 2.5 2.0 1.5 1.0 0.5 ...
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AD9211 EQUIVALENT CIRCUITS AVDD 1.2V 10kΩ 10kΩ CLK+ Figure 33. Clock Inputs AVDD VIN+ BUF 2kΩ BUF AVDD 2kΩ VIN– BUF Figure 34. Analog Inputs (V CML 1kΩ SCLK/DFS RESET 30kΩ PWDN Figure 35. Equivalent SCLK/DFS, RESET, PWDN Input Circuit ...
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THEORY OF OPERATION The AD9211 architecture consists of a front-end sample and hold amplifier (SHA) followed by a pipelined switched capacitor ADC. The quantized outputs from each stage are combined into a final 10-bit result in the digital correction logic. ...
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AD9211 CLOCK INPUT CONSIDERATIONS For optimum performance, the AD9211 sample clock inputs (CLK+ and CLK−) should be clocked with a differential signal. This signal is typically ac-coupled into the CLK+ pin and CLK− pin via a transformer or capacitors. These ...
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Clock Jitter Considerations High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input frequency (f ) due only to aperture jitter (t ) can be calculated by A ...
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AD9211 600 12 400 10 200 –200 4 –400 2 –600 0 –3 –2 – –100 TIME (ns) Figure 49. Data Eye for LVDS Outputs in ANSI Mode with Trace Lengths Greater than ...
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Table 9. Serial Port Pins Mnemonic Function SCLK SCLK (Serial Clock) is the serial shift clock in. SCLK is used to synchronize serial interface reads and writes. SDIO SDIO (Serial Data Input/Output dual-purpose pin. The typical role for ...
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AD9211 Table 11. Serial Timing Definitions Parameter Timing (minimum, ns CLK EN_SDIO t 5 DIS_SDIO Table 12. Output ...
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MEMORY MAP READING THE MEMORY MAP TABLE Each row in the memory map table has eight address locations. The memory map is roughly divided into three sections: chip configuration register map (Address 0x00 to Address 0x02), transfer register map (Address ...
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AD9211 Addr. Bit 7 (Hex) Parameter Name (MSB) Bit 6 ADC Functions 08 modes clock test_io OF ain_config output_mode 0 15 output_adjust output_phase Output 0 clock polarity 1 ...
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Addr. Bit 7 (Hex) Parameter Name (MSB) Bit 6 17 flex_output_delay Output delay enable enable 1 = disable 18 flex_vref 2A ovr_config Bit 5 Bit 4 Bit 3 Bit 2 Output clock delay: 00000 = 0.1 ns 00001 ...
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... Package Description 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] LVDS Evaluation Board with AD9211BCPZ-200 LVDS Evaluation Board with AD9211BCPZ-250 LVDS Evaluation Board with AD9211BCPZ-300 D06041-0-5/07(0) Rev Page 0.30 ...