AD9248BCPZ-40 Analog Devices Inc, AD9248BCPZ-40 Datasheet

IC,A/D CONVERTER,DUAL,14-BIT,CMOS,LLCC,64PIN

AD9248BCPZ-40

Manufacturer Part Number
AD9248BCPZ-40
Description
IC,A/D CONVERTER,DUAL,14-BIT,CMOS,LLCC,64PIN
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD9248BCPZ-40

Number Of Bits
14
Sampling Rate (per Second)
40M
Data Interface
Parallel
Number Of Converters
2
Power Dissipation (max)
330mW
Voltage Supply Source
Single Supply
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LFCSP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AD9248BST-65EBZ - BOARD EVAL WITH AD9248BST-65AD9248BCP-65EBZ - BOARD EVAL WITH AD9248BCP-65
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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AD9248BCPZ-40
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Part Number:
AD9248BCPZ-40
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ADI
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FEATURES
Integrated dual 14-bit ADC
Single 3 V supply operation (2.7 V to 3.6 V)
SNR = 71.6 dB (to Nyquist, AD9248-65)
SFDR = 80.5 dBc (to Nyquist, AD9248-65)
Low power: 300 mW/channel at 65 MSPS
Differential input with 500 MHz, 3 dB bandwidth
Exceptional crosstalk immunity > 85 dB
Flexible analog input: 1 V p-p to 2 V p-p range
Offset binary or twos complement data format
Clock duty cycle stabilizer
Output datamux option
APPLICATIONS
Ultrasound equipment
Direct conversion or IF sampling receivers
Battery-powered instruments
Hand-held scopemeters
Low cost digital oscilloscopes
GENERAL DESCRIPTION
The AD9248 is a dual, 3 V, 14-bit, 20 MSPS/40 MSPS/65 MSPS
analog-to-digital converter (ADC). It features dual high
performance sample-and hold amplifiers (SHAs) and an
integrated voltage reference. The AD9248 uses a multistage
differential pipelined architecture with output error correction
logic to provide 14-bit accuracy and to guarantee no missing
codes over the full operating temperature range at up to
65 MSPS data rates. The wide bandwidth, differential SHA
allows for a variety of user-selectable input ranges and offsets,
including single-ended applications. It is suitable for various
applications, including multiplexed systems that switch full-
scale voltage levels in successive channels and for sampling
inputs at frequencies well beyond the Nyquist rate.
Dual single-ended clock inputs are used to control all internal
conversion cycles. A duty cycle stabilizer is available and can
compensate for wide variations in the clock duty cycle, allowing
the converter to maintain excellent performance. The digital
output data is presented in either straight binary or twos
complement format. Out-of-range signals indicate an overflow
condition, which can be used with the most significant bit to
determine low or high overflow.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
WB-CDMA, CDMA2000, WiMAX
14-Bit, 20 MSPS/40 MSPS/65 MSPS
Fabricated on an advanced CMOS process, the AD9248 is
available in a Pb-free, space saving, 64-lead LQFP or LFCSP and
is specified over the industrial temperature range (−40°C to
+85°C).
PRODUCT HIGHLIGHTS
1. Pin-compatible with the AD9238, 12-bit 20 MSPS/
2. Speed grade options of 20 MSPS, 40 MSPS, and 65 MSPS
3. Low power consumption: AD9248-65: 65 MSPS = 600 mW,
4. Typical channel isolation of 85 dB @ f
5. The clock duty cycle stabilizer (AD9248-20/AD9248-40/
6. Multiplexed data output option enables single-port operation
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113 ©2005–2010 Analog Devices, Inc. All rights reserved.
REFB_B
REFB_A
REFT_B
REFT_A
VIN+_B
VIN–_B
VIN+_A
VIN–_A
SENSE
40 MSPS/65 MSPS ADC.
allow flexibility between power, cost, and performance to suit
an application.
AD9248-40: 40 MSPS = 330 mW, and AD9248-20: 20 MSPS =
180 mW.
AD9248-65) maintains performance over a wide range of
clock duty cycles.
from either Data Port A or Data Port B.
AGND
VREF
AD9248
FUNCTIONAL BLOCK DIAGRAM
SHA
SHA
0.5V
Dual A/D Converter
DRVDD DRGND
ADC
ADC
AVDD
Figure 1.
14
14
AGND
DUTY CYCLE
STABILIZER
CONTROL
BUFFERS
BUFFERS
OUTPUT
OUTPUT
CLOCK
MODE
MUX/
MUX/
IN
= 10 MHz.
14
14
www.analog.com
AD9248
CLK_A
OTR_A
MUX_SELECT
CLK_B
DCS
SHARED_REF
PWDN_A
PWDN_B
DFS
D13_B TO D0_B
D13_A TO D0_A
OTR_B
OEB_A
OEB_B

Related parts for AD9248BCPZ-40

AD9248BCPZ-40 Summary of contents

Page 1

FEATURES Integrated dual 14-bit ADC Single 3 V supply operation (2 3.6 V) SNR = 71.6 dB (to Nyquist, AD9248-65) SFDR = 80.5 dBc (to Nyquist, AD9248-65) Low power: 300 mW/channel at 65 MSPS Differential input with 500 ...

Page 2

AD9248 TABLE OF CONTENTS Specifications ..................................................................................... 3 DC Specifications ......................................................................... 3 AC Specifications .......................................................................... 5 Digital Specifications ................................................................... 6 Switching Specifications .............................................................. 7 Absolute Maximum Ratings ............................................................ 8 Explanation of Test Levels ........................................................... 8 ESD Caution .................................................................................. 8 Pin Configurations ...

Page 3

SPECIFICATIONS DC SPECIFICATIONS AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B DCS enabled, unless otherwise noted. MIN MAX Table 1. Parameter Temp RESOLUTION Full ACCURACY No Missing Codes Guaranteed ...

Page 4

AD9248 Parameter Temp MATCHING CHARACTERISTICS Offset Error 25°C (Nonshared Reference Mode) Offset Error 25°C (Shared Reference Mode) Gain Error 25°C (Nonshared Reference Mode) Gain Error 25°C (Shared Reference Mode) 1 Gain error and gain temperature coefficient are based on the ...

Page 5

AC SPECIFICATIONS AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B DCS Enabled, unless otherwise noted. MIN MAX Table 2. Parameter SIGNAL-TO-NOISE RATIO (SNR 2.4 MHz INPUT f ...

Page 6

AD9248 Parameter WORST OTHER SPUR (NONSECOND or THIRD 2.4 MHz INPUT f = 9.7 MHz INPUT f = 19.6 MHz INPUT MHz INPUT f = 100 MHz INPUT SPURIOUS-FREE DYNAMIC RANGE (SFDR 2.4 ...

Page 7

SWITCHING SPECIFICATIONS AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B DCS enabled, unless otherwise noted. MIN MAX Table 4. Parameter Temp SWITCHING PERFORMANCE Maximum Conversion Rate Full Minimum Conversion ...

Page 8

AD9248 ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended ...

Page 9

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS AGND VIN+_A VIN–_A AGND AVDD REFT_A REFB_A VREF SENSE REFB_B REFT_B AVDD AGND VIN–_B VIN+_B AGND VIN+_A VIN–_A REFT_A REFB_A SENSE REFB_B REFT_B VIN–_B VIN+ ...

Page 10

AD9248 Table 6. 64-Lead LQFP and 64-Lead LFCSP Pin Function Descriptions Pin No. Mnemonic Description 1, 4, 13, 16 AGND Analog Ground. 2 VIN+_A Analog Input Pin (+) for Channel A. 3 VIN−_A Analog Input Pin (−) for Channel A. ...

Page 11

TERMINOLOGY Aperture Delay SHA performance measured from the rising edge of the clock input to when the input signal is held for conversion. Aperture Jitter The variation in aperture delay for successive samples, which is manifested as noise on the ...

Page 12

AD9248 TYPICAL PERFORMANCE CHARACTERISTICS AVDD, DRVDD = 3 25° –20 –40 –60 –80 SECOND CROSSTALK HARMONIC –100 –120 FREQUENCY (MHz) Figure 5. Single-Tone FFT of Channel A Digitizing f ...

Page 13

SFDR SNR 80 70 SNR –35 –30 –25 –20 –15 –10 INPUT AMPLITUDE (dBFS) Figure 11. AD9248-65 Single-Tone SFDR/SNR vs. A 100 90 80 SNR SFDR 70 SNR –35 –30 –25 –20 ...

Page 14

AD9248 0 –20 –40 –60 IMD = –85dBc –80 –100 –120 FREQUENCY (MHz) Figure 17. Dual-Tone FFT with MHz and –20 –40 IMD = –83dBc –60 –80 –100 ...

Page 15

SINAD –20 72 SINAD –65 SINAD – CLOCK FREQUENCY (MHz) Figure 23. SINAD vs. FS with Nyquist Input 95 DCS ON (SFDR DCS OFF (SFDR DCS ON (SINAD ...

Page 16

AD9248 EQUIVALENT CIRCUITS AVDD VIN+_A, VIN–_A, VIN+_B, VIN–_B Figure 29. Equivalent Analog Input Circuit DRVDD Figure 30. Equivalent Digital Output Circuit AVDD CLK_A, CLK_B DCS, DFS, MUX_SELECT, SHARED_REF Figure 31. Equivalent Digital Input Circuit Rev Page 16 of ...

Page 17

THEORY OF OPERATION The AD9248 consists of two high performance ADCs that are based on the AD9235 converter core. The dual ADC paths are independent, except for a shared internal band gap reference source, VREF. Each of the ADC paths ...

Page 18

AD9248 The minimum common-mode input level allows the AD9248 to accommodate ground-referenced inputs. Although optimum performance is achieved with a differential input, a single-ended source may be driven into VIN+ or VIN−. In this configuration, one input accepts the signal, ...

Page 19

POWER DISSIPATION AND STANDBY MODE The power dissipated by the AD9248 is proportional to its sampling rates. The digital (DRVDD) power dissipation is determined primarily by the strength of the digital drivers and the load on each output bit. The ...

Page 20

AD9248 DATA FORMAT The AD9248 data output format can be configured for either twos complement or offset binary. This is controlled by the data format select pin (DFS). Connecting DFS to AGND produces offset binary output data. Conversely, connecting DFS ...

Page 21

External Reference Operation The use of an external reference may be necessary to enhance the gain accuracy of the ADC or to improve thermal drift characteristics. When multiple ADCs track one another, a single reference (internal or external) may be ...

Page 22

AD9248 AD9248 LQFP EVALUATION BOARD The evaluation board supports both the AD9238 and AD9248 and has five main sections: clock circuitry, inputs, reference circuitry, digital control logic, and outputs. A description of each section follows. Table 8 shows the jumper ...

Page 23

Table 8. PCB Jumpers Normal JP Description Setting Comment 1 Reference Out 1 V Reference Mode 2 Reference Reference Mode 3 Reference Out 1 V Reference Mode 4 Reference Out 1 V Reference Mode 5 Reference Out ...

Page 24

AD9248 LQFP EVALUATION BOARD BILL OF MATERIALS (BOM) Table 10. No. Quantity Reference Designator 1 18 C1, C2, C11, C12, C27, C28, C33, C34, C50, C51, C73 to C76, C87 to C90 C10, C29 to C31, ...

Page 25

LQFP EVALUATION BOARD SCHEMATICS Figure 40. Evaluation Board Schematic Rev Page AD9248 ...

Page 26

AD9248 Figure 41. Evaluation Board Schematic (Continued) Rev Page ...

Page 27

Figure 42. Evaluation Board Schematic (Continued) Rev Page AD9248 ...

Page 28

AD9248 C75 C3 C10 10μF 0.1μF 0.1μF 6.3V DATACLKA 1 RP9 22Ω RP9 22Ω 7 OTRA 3 RP9 22Ω 6 DA13 4 RP9 22Ω 5 DA12 1 RP10 22Ω 8 DA11 2 RP10 22Ω 7 DA10 3 RP10 ...

Page 29

LQFP PCB LAYERS Figure 44. PCB Top Layer Rev Page AD9248 ...

Page 30

AD9248 Figure 45. Bottom Layer Rev Page ...

Page 31

Figure 46. PCB Ground Plane Rev Page AD9248 ...

Page 32

AD9248 Figure 47. PCB Split Power Plane Rev Page ...

Page 33

Figure 48. PCB Top Silkscreen (Note that the PCB Supports Both the AD9238 and AD9248 LQFP) Rev Page AD9248 ...

Page 34

AD9248 Figure 49. PCB Bottom Silkscreen Rev Page ...

Page 35

DUAL ADC LFCSP PCB The PCB requires a low jitter clock source, analog sources, and power supplies. The PCB interfaces directly with Analog Devices standard dual-channel data capture board (HSC-ADC-EVAL-DC), which together with ADI’s ADC Analyzer™ software allows for quick ...

Page 36

AD9248 LFCSP EVALUATION BOARD BILL OF MATERIALS (BOM) Table 13. No. Quantity Reference Designator C2, C5, C7, C9, C10, C22, C36 3 44 C4, C6, C8, C11 to C15, C20, C21, C24 to C27, ...

Page 37

LFCSP PCB SCHEMATICS ENCA D7A D7_A 49 D8A D8_A 50 D9A D9_A 51 DRVDD2 52 DRGND2 53 D10A D10_A 54 D11A D11_A 55 D12A D12_A 56 D13A D13_A 57 OTRA OTR_A 58 OEB_A 59 PDWN_A 60 MUX_SEL 61 SH_REF 62 ...

Page 38

AD9248 Figure 51. PCB Schematic ( Rev Page ...

Page 39

Figure 52. PCB Schematic ( Rev Page AD9248 ...

Page 40

AD9248 LFCSP PCB LAYERS Figure 53. PCB Top-Side Silkscreen Rev Page ...

Page 41

Figure 54. PCB Top-Side Copper Routing Rev Page AD9248 ...

Page 42

AD9248 Figure 55. PCB Ground Layer Rev Page ...

Page 43

Figure 56. PCB Split Power Plane Rev Page AD9248 ...

Page 44

AD9248 Figure 57. PCB Bottom-Side Copper Routing Rev Page ...

Page 45

THERMAL CONSIDERATIONS The AD9248 LFCSP has an integrated heat slug that improves the thermal and electrical properties of the package when locally attached to a ground plane at the PCB. A thermal (filled) via array to a ground plane beneath ...

Page 46

AD9248 OUTLINE DIMENSIONS 1.45 1.40 1.35 0.15 SEATING 0.05 PLANE VIEW A ROTATED 90° CCW BSC SQ PIN 1 INDICATOR 1.00 12° MAX 0.85 0.80 SEATING PLANE 0.75 1.60 0.60 MAX 0. PIN 1 0.20 0.09 7° 3.5° ...

Page 47

... AD9248BSTZRL-20 –40°C to +85°C AD9248BSTZRL-40 –40°C to +85°C AD9248BSTZRL-65 –40°C to +85°C AD9248BCPZ-20 –40°C to +85°C AD9248BCPZ-40 –40°C to +85°C AD9248BCPZ-65 –40°C to +85°C AD9248BCPZRL-20 –40°C to +85°C AD9248BCPZRL-40 –40°C to +85°C AD9248BCPZRL-65 – ...

Page 48

AD9248 NOTES ©2005–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04446–0–11/10(B) Rev Page ...

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