AD9261-10EBZ Analog Devices Inc, AD9261-10EBZ Datasheet - Page 4

• Manufacturer Part Number: AD9261-10EBZ
• Description: 16Bit 10 MHz Sigma Delta ADC EB
• Manufacturer: Analog Devices Inc

Specifications of AD9261-10EBZ

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9261
CONFIGURING THE EVALUATION BOARD
POWER SUPPLY
Power is provided to the evaluation board by a single +6.0 V
source applied to P2. The power source is regulated down to the
appropriate levels by the ADP3339 voltage regulators. Table 2
shows the necessary voltage levels for each component.
Table 2. Component Power Supplies
Component
AD9261
ADA4937-1
AD9516-0
CLOCK
The AD9261 evaluation board offers many clocking options:
a high frequency external clock can be applied directly to the
ADC; the AD9516-0 LVPECL or CMOS clock can be used; and
a low frequency clock, in conjunction with the integrated PLL
from either the AD9516-0 or AD9261, can provide the necessary
input clock frequency. The default clock option is configured
for an external clock rate of 640 MHz.
The AD9261 evaluation board includes the footprint for a
Valpey Fisher VFAC3 crystal oscillator. The crystal oscillator
can serve as the reference clock to the AD9516-0, and the chip’s
internal PLL can be used to generate a clock closest to the desired
frequency for the ADC. For example, a 122.88 MHz reference
produces a VCO frequency of 2.580 GHz.
The AD9516-0 possesses an integrated VCO. The VCO fre-
quency is further divided down by 4 to generate an output clock
of 645 MHz, which serves as the input clock to the ADC. To
optimize the AD9516-0 for this particular frequency, the loop
filter must be configured as shown in Figure 5.
If the user chooses an alternative crystal oscillator frequency,
the loop filter components must be configured appropriately.
Some common crystal oscillators and the corresponding loop
filter components are shown in Table 3. Refer to the ADIsimCLK
software for design guidance.
CP
1000pF
C107
0Ω
Figure 5: AD9516-0 Loop Filter
R11
280Ω
C31
15,000pF
576Ω
R25
Power Supply
1.8 V
5.0 V
3.3 V
C108
560pF
R26
0Ω
LF
BYPASS_LDO
Rev. PrA | Page 4 of 20
Table 3. AD9516-0 CLK Configuration
Crystal
(MHz)
134.4
122.88
39.3216 1500 pF 221 Ω
To configure the evaluation board for either the external clock
source or the AD9516-0 requires modifying the JP2 and JP5
solder jumpers. The AD9261 sets the common-mode level of
the input clock to 450 mV; therefore, the clock source should be
ac-coupled to the ADC input clock pins. Use the AD9516-0
software to configure the chip to the appropriate divide ratios.
DIFFERENTIAL TRANSFORMER PATH
The differential transformer path is the default configuration.
Table 4 shows the jumper settings for this configuration.
Table 4: Differential Transformer Configuration
Jumper
JP1
JP3
JP4
AMPLIFIER DRIVER PATH
To configure the evaluation board for the ADA4937-1 driver
amplifier, set the jumpers as shown in Table 5.
Table 5: ADA4937 Configuration
Jumper
JP1
JP3
JP4
C107
1000 pF 232 Ω
1000 pF 280 Ω
Setting
Short Position 2 and
Position 3
Short Position 1 and
Position 2
Short Position 2 and
Position 3
Setting
Short Position 1 and
Position 2
Short Position 2 and
Position 3
Short Position 1 and
Position 2
R11
Preliminary Technical Data
Loop Filter
C31
18,000 pF 486 Ω 680 pF
15,000 pF 576 Ω 560 pF
22,000 pF 453 Ω 680 pF
Notes
Configure SMA connectors for
the transformer inputs
Configure differential
transformer outputs to ADC
inputs
Notes
Configure the SMA connectors
for the ADA4937 inputs
Configure outputs from the
ADA4937 to ADC inputs
R13
C108
AD9261
CLK
672
645.12
648.8
MHz
MHz
MHz