AD9517-1ABCPZ Analog Devices Inc, AD9517-1ABCPZ Datasheet - Page 18

• Manufacturer Part Number: AD9517-1ABCPZ
• Description: 12-Output Clock Generator With 2.5GHz VC
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9517-1ABCPZ

• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVDS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 1:12
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.65GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Frequency-max: 2.65GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9517-1
Pin No.
13
14
15
16
17
18
21, 40
42
41
39
38
19
20
22
23
35
34
33
32
26
27
28
29
44
46
47
48
EPAD
Input/
Output
I
I
O
I/O
I
I
I
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
Pin Type
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
Power
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVDS or
CMOS
LVDS or
CMOS
LVDS or
CMOS
LVDS or
CMOS
LVDS or
CMOS
LVDS or
CMOS
LVDS or
CMOS
LVDS or
CMOS
Current set
resistor
Current set
resistor
Reference
input
Reference
input
GND
Mnemonic
SCLK
CS
SDO
SDIO
RESET
PD
VS_LVPECL
OUT0
OUT0
OUT1
OUT1
OUT2
OUT2
OUT3
OUT3
OUT4 (OUT4A)
OUT4 (OUT4B)
OUT5 (OUT5A)
OUT5 (OUT5B)
OUT6 (OUT6A)
OUT6 (OUT6B)
OUT7 (OUT7A)
OUT7 (OUT7B)
RSET
CPRSET
REFIN (REF2)
REFIN (REF1)
GND
Description
Serial Control Port Data Clock Signal.
Serial Control Port Chip Select; Active Low. This pin has an internal 30 kΩ pull-up
resistor.
Serial Control Port Unidirectional Serial Data Out.
Serial Control Port Bidirectional Serial Data In/Out.
Chip Reset, Active Low. This pin has an internal 30 kΩ pull-up resistor.
Chip Power Down, Active Low. This pin has an internal 30 kΩ pull-up resistor.
Extended Voltage 2.5 V to 3.3 V LVPECL Power Pins.
LVPECL Output; One Side of a Differential LVPECL Output.
LVPECL Output; One Side of a Differential LVPECL Output.
LVPECL Output; One Side of a Differential LVPECL Output.
LVPECL Output; One Side of a Differential LVPECL Output.
LVPECL Output; One Side of a Differential LVPECL Output.
LVPECL Output; One Side of a Differential LVPECL Output.
LVPECL Output; One Side of a Differential LVPECL Output.
LVPECL Output; One Side of a Differential LVPECL Output.
LVDS/CMOS Output; One Side of a Differential LVDS Output
or a Single-Ended CMOS Output.
LVDS/CMOS Output; One Side of a Differential LVDS Output
or a Single-Ended CMOS Output.
LVDS/CMOS Output; One Side of a Differential LVDS Output
or a Single-Ended CMOS Output.
LVDS/CMOS Output; One Side of a Differential LVDS Output
or a Single-Ended CMOS Output.
LVDS/CMOS Output; One Side of a Differential LVDS Output
or a Single-Ended CMOS Output.
LVDS/CMOS Output; One Side of a Differential LVDS Output
or a Single-Ended CMOS Output.
LVDS/CMOS Output; One Side of a Differential LVDS Output
or a Single-Ended CMOS Output.
LVDS/CMOS Output; One Side of a Differential LVDS Output
or a Single-Ended CMOS Output.
Resistor connected here sets internal bias currents. Nominal value = 4.12 kΩ.
Resistor connected here sets CP current range. Nominal value = 5.1 kΩ.
Along with REFIN, this is the self-biased differential input for the PLL reference.
Alternatively, this pin is a single-ended input for REF2.
Along with REFIN, this is the self-biased differential input for the PLL reference.
Alternatively, this pin is a single-ended input for REF1.
Ground. The external paddle on the bottom of the package must be connected to
ground for proper operation.
Rev. B | Page 18 of 80