AD9518-1A/PCBZ Analog Devices Inc, AD9518-1A/PCBZ Datasheet - Page 14

• Manufacturer Part Number: AD9518-1A/PCBZ
• Description: 6-Output Clock Generator With 2.8GHz
• Manufacturer: Analog Devices Inc

Specifications of AD9518-1A/PCBZ

• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9518-1A
• Primary Attributes: 2 Inputs, 6 Outputs, 2.5GHz VCO
• Secondary Attributes: LVPECL Output Logic
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9518-1
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 19. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10, 24, 25,
26, 35, 37,
43, 45
11
12
Input/
Output
I
O
I
O
O
I
I
I
O
I
I
I
Pin Type
3.3 V CMOS
3.3 V CMOS
Power
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
Loop filter
Loop filter
Power
Differential
clock input
Differential
clock input
REF_SEL
NOTES
1. NC = NO CONNECT.
2. THE EXTERNAL PADDLE ON THE BOTTOM OF THE PACKAGE MUST BE
REFMON
Mnemonic
REFMON
LD
VCP
CP
STATUS
REF_SEL
SYNC
LF
BYPASS
VS
CLK
CLK
BYPASS
STATUS
CONNECTED TO GROUND FOR PROPER OPERATION.
SYNC
VCP
CLK
CLK
CP
LD
VS
LF
10
11
12
1
2
3
4
5
6
7
8
9
Description
Reference Monitor (Output). This pin has multiple selectable outputs; see Table 44,
Register 0x1B.
Lock Detect (Output). This pin has multiple selectable outputs; see Table 44,
Register 0x1A.
Power Supply for Charge Pump (CP). V
Charge Pump (Output). Connects to external loop filter.
Status (Output). This pin has multiple selectable outputs; see Table 44, Register 0x17.
Reference Select. Selects REF1 (low) or REF2 (high). This pin has an internal 30 kΩ
pull-down resistor.
Manual Synchronizations and Manual Holdover. This pin initiates a manual
synchronization and is also used for manual holdover. Active low. This pin has an
internal 30 kΩ pull-up resistor.
Loop Filter (Input). Connects to VCO control voltage node internally.
This pin has 31 pF of internal capacitance to ground, which may influence the loop
filter design for large loop bandwidths.
This pin is for bypassing the LDO to ground with a capacitor.
3.3 V Power Pins.
Along with CLK, this is the self-biased differential input for the clock distribution section.
Along with CLK, this is the self-biased differential input for the clock distribution section.
PIN 1
INDICATOR
Figure 4. Pin Configuration
Rev. A | Page 14 of 64
(Not to Scale)
AD9518-1
TOP VIEW
36
35
34
33
32
31
30
29
28
27
26
25
VS_LVPECL
VS_LVPECL
OUT3
OUT2
OUT2
OUT3
S
≤ V
CP
≤ 5.0 V.