AD9518-1BCPZ Analog Devices Inc, AD9518-1BCPZ Datasheet - Page 39

• Manufacturer Part Number: AD9518-1BCPZ
• Description: IC,Six Distributed-Output Clock Driver,LLCC,48PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9518-1BCPZ

• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 1:6
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.65GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Frequency-max: 2.65GHz
• Function: Clock Generator
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: LFCSP EP
• Pin Count: 48
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9518-1/PCBZ - BOARD EVAL FOR AD9518-1
• Lead Free Status / Rohs Status: Compliant

If the AD9518 clock outputs must be synchronized to each
other, a SYNC is required upon exiting power-down (see the
Synchronizing the Outputs—SYNC Function section). A VCO
calibration is not required when exiting power-down.
PLL Power-Down
The PLL section of the AD9518 can be selectively powered down.
There are three PLL operating modes set by Register 0x010[1:0],
as shown in Table 44.
In asynchronous power-down mode, the device powers down as
soon as the registers are updated.
In synchronous power-down mode, the PLL power-down is
gated by the charge pump to prevent unwanted frequency jumps.
The device goes into power-down on the occurrence of the next
charge pump event after the registers are updated.
Distribution Power-Down
The distribution section can be powered down by writing
Register 0x230[1] = 1b. This turns off the bias to the distribution
section. If the LVPECL power-down mode is normal operation
(00b), it is possible for a low impedance load on that LVPECL
output to draw significant current during this power-down.
If the LVPECL power-down mode is set to 11b, the LVPECL
output is not protected from reverse bias and may be damaged
under certain termination conditions.
Rev. A | Page 39 of 64
Individual Clock Output Power-Down
Any of the clock distribution outputs can be powered down
individually by writing to the appropriate registers. The register
map details the individual power-down settings for each output.
The LVPECL outputs have multiple power-down modes
(see Table 45), which give some flexibility in dealing with the
various output termination conditions. When the mode is set to
10b, the LVPECL output is protected from reverse bias to
2 VBE + 1 V. If the mode is set to 11b, the LVPECL output is
not protected from reverse bias and can be damaged under
certain termination conditions. This setting also affects the
operation when the distribution block is powered down with
Register 0x230[1] = 1b (see the Distribution Power-Down
section).
Individual Circuit Block Power-Down
Other AD9518 circuit blocks (such as CLK, REF1, and REF2)
can be powered down individually. This gives flexibility in
configuring the part for power savings whenever certain chip
functions are not needed.
AD9518-1