AD9518-2BCPZ Analog Devices Inc, AD9518-2BCPZ Datasheet - Page 2

• Manufacturer Part Number: AD9518-2BCPZ
• Description: IC,Six Distributed-Output Clock Driver,LLCC,48PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9518-2BCPZ

• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 1:6
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.33GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Frequency-max: 2.33GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9518-2/PCBZ - BOARD EVAL FOR AD9518-2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9518-2
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
Specifications ..................................................................................... 4
Timing Diagrams ............................................................................ 12
Absolute Maximum Ratings .......................................................... 13
Power Supply Requirements ....................................................... 4
PLL Characteristics ...................................................................... 4
Clock Inputs .................................................................................. 6
Clock Outputs ............................................................................... 6
Timing Characteristics ................................................................ 6
Clock Output Additive Phase Noise (Distribution Only;
VCO Divider Not Used) .............................................................. 7
Clock Output Absolute Phase Noise (Internal VCO Used) .... 7
Clock Output Absolute Time Jitter (Clock Generation
Using Internal VCO) .................................................................... 8
Clock Output Absolute Time Jitter (Clock Cleanup
Using Internal VCO) .................................................................... 8
Clock Output Absolute Time Jitter (Clock Generation
Using External VCXO) ................................................................ 8
Clock Output Additive Time Jitter (VCO Divider
Not Used) ....................................................................................... 9
Clock Output Additive Time Jitter (VCO Divider Used) ....... 9
Serial Control Port ..................................................................... 10
PD , SYNC , and RESET Pins ..................................................... 10
LD, STATUS, and REFMON Pins ............................................ 11
Power Dissipation ....................................................................... 11
Rev. A | Page 2 of 64
Pin Configuration and Function Descriptions ........................... 14
Typical Performance Characteristics ........................................... 16
Terminology .................................................................................... 20
Detailed Block Diagram ................................................................ 21
Theory of Operation ...................................................................... 22
Serial Control Port ......................................................................... 40
Thermal Performance .................................................................... 44
Control Registers ............................................................................ 45
Applications Information .............................................................. 60
Outline Dimensions ....................................................................... 62
Thermal Resistance .................................................................... 13
ESD Caution................................................................................ 13
Operational Configurations ...................................................... 22
Digital Lock Detect (DLD) ....................................................... 30
Clock Distribution ..................................................................... 34
Reset Modes ................................................................................ 38
Power-Down Modes .................................................................. 38
Serial Control Port Pin Descriptions ....................................... 40
General Operation of Serial Control Port ............................... 40
The Instruction Word (16 Bits) ................................................ 41
MSB/LSB First Transfers ........................................................... 41
Control Register Map Overview .............................................. 45
Control Register Map Descriptions ......................................... 47
Frequency Planning Using the AD9518 .................................. 60
Using the AD9518 Outputs for ADC Clock Applications .... 60
LVPECL Clock Distribution ..................................................... 61
Ordering Guide .......................................................................... 62