AD9520-5BCPZ-REEL7 Analog Devices Inc, AD9520-5BCPZ-REEL7 Datasheet - Page 37

• Manufacturer Part Number: AD9520-5BCPZ-REEL7
• Description: 12/24-Output Clock Generator
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9520-5BCPZ-REEL7

• Design Resources: Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186)
• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 2:12, 2:24
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.4GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 1.6GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

After leaving holdover, the loop then reacquires lock, and the
LD pin must go high (if 0x01D[3] = 1) before it can reenter
holdover.
The holdover function always responds to the state of the
currently selected reference (0x01C). If the loop loses lock
during a reference switchover (see the Reference Switchover
section), holdover is triggered briefly until the next reference
clock edge at the PFD.
The following registers affect the automatic/internal holdover
function:
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•
•
•
•
•
OPTIONAL
0x018[6:5]—lock detect counter. This changes how many
consecutive PFD cycles with edges inside the lock detect
window are required for the DLD indicator to indicate
lock. This impacts the time required before the LD pin can
begin to charge as well as the delay from the end of a
holdover event until the holdover function can be reengaged.
0x018[3]—disable digital lock detect. This bit must be set
to 0 to enable the DLD circuit. Internal/automatic holdover
does not operate correctly without the DLD function enabled.
0x01A[5:0]—lock detect pin control. Set this to 000100b to
put it in the current source lock detect mode if using the
LD pin comparator. Load the LD pin with a capacitor of an
appropriate value.
0x01D[3]—LD pin comparator enable. 1 = enable; 0 =
disable. When disabled, the holdover function always
senses the LD pin as high.
0x01D[1]—external holdover control.
0x01D[0]—holdover enable. If holdover is disabled, both
external and automatic internal holdover are disabled.
REFIN
REFIN
CLK
CLK
REF1
REF2
BUF
SWITCHOVER
STATUS
REFERENCE
REF_SEL
STATUS
VS
PRESCALER
ZERO DELAY BLOCK
CLK FREQUENCY STATUS
2, 3, 4, 5, OR 6
DIVIDE BY 1,
1
P, P + 1
GND
0
Figure 35. Reference and VCO Status Monitors
N DIVIDER
COUNTERS
DISTRIBUTION
REFERENCE
A/B
Rev. 0 | Page 37 of 80
RSET
FROM CHANNEL
PROGRAMMABLE
DIVIDER 0
REFMON
For example, if the user wants to configure automatic holdover with
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•
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The following registers are set (in addition to the normal PLL
registers):
•
•
•
•
•
•
•
•
•
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Frequency Status Monitors
The AD9520 contains three frequency status monitors that are
used to indicate if the PLL reference (or references in the case of
single-ended mode) and the VCO have fallen below a threshold
frequency. A diagram showing their location in the PLL is
shown in Figure 35.
The PLL reference monitors have two threshold frequencies:
normal and extended (see Table 14). The reference frequency
monitor thresholds are selected in 0x01F.
N DELAY
Automatic reference switchover, prefer REF1.
Digital lock detect: five PFD cycles, high range window.
Automatic holdover using the LD pin comparator.
0x018[6:5] = 00b; lock detect counter = five cycles.
0x018[4] = 0b; digital lock detect window = high range.
0x018[3] = 1b; disable DLD normal operation.
0x01A[5:0] = 000100b; program LD pin control to current
source lock detect mode.
0x01C[4] = 1b; enable automatic switchover.
0x01C[3] = 0b; prefer REF1.
0x01C[2:1] = 11b; enable REF1 and REF2 input buffers.
0x01D[3] = 1b; enable LD pin comparator.
0x01D[1] = 0b; disable external holdover mode and use
automatic/internal holdover mode.
0x01D[0] = 1b; enable holdover.
FREQUENCY
DETECTOR
DETECT
PHASE
LOCK
CPRSET VCP
CHARGE
PUMP
HOLD
AD9520-5
LD
CP
STATUS
VS_DRV