AD9609-65EBZ Analog Devices Inc, AD9609-65EBZ Datasheet - Page 10

• Manufacturer Part Number: AD9609-65EBZ
• Description: 10 Bit 65 Msps Low Pwr ADC
• Manufacturer: Analog Devices Inc

Specifications of AD9609-65EBZ

• Number Of Adc's: 1
• Number Of Bits: 10
• Sampling Rate (per Second): 65M
• Data Interface: Serial, SPI™
• Inputs Per Adc: 1 Differential
• Input Range: 2 Vpp
• Power (typ) @ Conditions: 73.3mW @ 65MSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9609
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9609
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 8. Pin Function Descriptions
Pin No.
0 (Exposed Pad)
1, 2
3, 24, 29, 32
4
5
6
7 to 10
11 to 12, 14 to 21
13
22
23
25
26
27
28
30, 31
Mnemonic
AGND
CLK+, CLK−
AVDD
CSB
SCLK/DFS
SDIO/PDWN
NC
D0 (LSB) to
D9 (MSB)
DRVDD
DCO
MODE/OR
VREF
SENSE
VCM
RBIAS
VIN−, VIN+
Description
The exposed paddle is the only ground connection. It must be soldered to the analog ground of the
PCB to ensure proper functionality and heat dissipation, noise, and mechanical strength benefits.
Differential Encode Clock for PECL, LVDS, or 1.8 V CMOS Inputs.
1.8 V Supply Pin for ADC Core Domain.
SPI Chip Select. Active low enable, 30 kΩ internal pull-up.
SPI Clock Input in SPI Mode (SCLK). 30 kΩ internal pull-down.
Data Format Select in Non-SPI Mode (DFS). Static control of data output format. 30 kΩ internal pull-down.
DFS high = twos complement output; DFS low = offset binary output.
SPI Data Input/Output (SDIO). Bidirectional SPI data I/O with 30 kΩ internal pull-down.
Non-SPI Mode Power-Down (PDWN). Static control of chip power-down with 30 kΩ internal pull-
down. See Table 15 for details.
Do not connect.
ADC Digital Outputs.
1.8 V to 3.3 V Supply Pin for Output Driver Domain.
Data Clock Digital Output.
Chip Mode Select Input (MODE)/Out-of-Range Digital Output in SPI Mode (OR).
Default = out-of-range (OR) digital output (SPI Register 0x2A, Bit 0 = 1).
Option = chip mode select input (SPI Register 0x2A, Bit 0 = 0).
Chip power-down (SPI Register 0x08, Bits[7:5] = 100b).
Chip stand-by (SPI Register 0x08, Bits[7:5] = 101b).
Normal operation, output disabled (SPI Register 0x08, Bits[7:5] = 110b).
Normal operation, output enabled (SPI Register 0x08, Bits[7:5] = 111b).
Out-of-range (OR) digital output only in non-SPI mode.
1.0 V Voltage Reference Input/Output. See Table 10.
Reference Mode Selection. See Table 10.
Analog Output Voltage at Mid AVDD Supply. Sets common mode of the analog inputs.
Set Analog Current Bias. Connect to 10 kΩ (1% tolerance) resistor to ground.
ADC Analog Inputs.
SDIO/PDWN
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PADDLE MUST BE SOLDERED TO
SCLK/DFS
THE PCB GROUND TO ENSURE PROPER HEAT DISSIPATION,
NOISE, AND MECHANICAL STRENGTH BENEFITS.
AVDD
CLK+
CLK–
CSB
NC
NC
1
2
3
4
5
6
7
8
Figure 3. Pin Configuration
(Not to Scale)
Rev. 0 | Page 10 of 32
PIN 1
INDICATOR
TOP VIEW
AD9609
24 AVDD
23 MODE/OR
22 DCO
21 D9 (MSB)
20 D8
19 D7
18 D6
17 D5