AD9753ASTZ Analog Devices Inc, AD9753ASTZ Datasheet
AD9753ASTZ
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AD9753ASTZ Summary of contents
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FEATURES 12-Bit Dual Muxed Port DAC 300 MSPS Output Update Rate Excellent SFDR and IMD Performance SFDR to Nyquist @ 25 MHz Output Internal Clock Doubling PLL Differential or Single-Ended Clock Input On-Chip 1.2 V Reference Single 3.3 ...
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AD9753–SPECIFICATIONS ( MIN DC SPECIFICATIONS otherwise noted.) Parameter RESOLUTION 1 DC ACCURACY Integral Linearity Error (INL) Differential Nonlinearity (DNL) ANALOG OUTPUT Offset Error Gain Error (Without Internal Reference) Gain Error (With Internal Reference) 2 Full-Scale Output Current Output ...
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DYNAMIC SPECIFICATIONS Parameter DYNAMIC PERFORMANCE Maximum Output Update Rate (f DAC Output Settling Time (t ) (to 0.1 Output Propagation Delay ( Glitch Impulse 1 Output Rise Time (10% to 90%) 1 Output Fall Time ...
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AD9753 DIGITAL SPECIFICATIONS Parameter DIGITAL INPUTS Logic 1 Logic 0 Logic 1 Current Logic 0 Current Input Capacitance Input Setup Time ( 25° Input Hold Time ( 25° Latch Pulsewidth ...
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ABSOLUTE MAXIMUM RATINGS* Parameter AVDD, DVDD, CLKVDD, PLLVDD AVDD, DVDD, CLKVDD, PLLVDD ACOM, DCOM, CLKCOM, PLLCOM REFIO, REFLO, FSADJ OUTA OUTB Digital Data Inputs (DB13 to DB0) CLK+/CLK–, PLLLOCK DIV0, DIV1, RESET LPF Junction Temperature Storage Temperature ...
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AD9753 MSB–P1B11 Pin No. Mnemonic 1 RESET 2 CLK+ 3 CLK– DCOM 5, 21 DVDD 6 PLLLOCK 7–18 P1B11–P1B0 19–20, 35–36 RESERVED 23–34 P2B11–P2B0 37, 38 DIV0, DIV1 39 REFIO 40 FSADJ 41 AVDD 42 I OUTB 43 ...
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TERMINOLOGY Linearity Error (Also Called Integral Nonlinearity or INL) Linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale. Differential Nonlinearity (DNL) ...
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AD9753–Typical Performance Characteristics 90 0dBmFS 80 70 –6dBmFS 60 –12dBmFS (MHz) OUT TPC 1. Single-Tone SFDR vs OUT MSPS, Single-Port Mode DAC 90 80 ...
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A (dBm) OUT TPC 10. Two-Tone IMD (to Nyquist) vs ...
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AD9753 3.0V TO 3.6V DVDD 1.2V REF PMOS CURRENT SOURCE ARRAY REFIO FSADJ 0 SET 2k AD9753 DCOM ACOM FUNCTIONAL DESCRIPTION Figure 3 shows a simplified block diagram of the AD9753. The AD9753 consists of a PMOS current ...
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REFERENCE CONTROL AMPLIFIER The AD9753 also contains an internal control amplifier that is used to regulate the DAC’s full-scale output current, I The control amplifier is configured as a voltage-to-current converter as shown in Figure 4, so that its current ...
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AD9753 reference clock that is twice the input data rate should consider disabling the PLL clock multiplier to achieve the best SNR performance from the AD9753. Note, the SFDR performance of the AD9753 remains unaffected with or without the PLL ...
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INTERLEAVED (2 ) MODE WITH PLL DISABLED The relationship between the internal and external clocks in this mode is shown in Figure 11. A clock at the output update data rate (2× the input data rate) must be applied to ...
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AD9753 Substituting the values OUTA OUTB, expressed as = {(2 DAC CODE – 4095)/4096} × V DIFF ) × LOAD SET REFIO These last two equations highlight some of the advantages of ...
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DIGITAL INPUT Figure 14. Equivalent Digital Input The AD9753 features a flexible differential clock input operat- ing from separate supplies (i.e., CLKVDD, CLKCOM) to achieve optimum jitter performance. The two clock inputs, CLK+ and CLK–, can be driven from a ...
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AD9753 and is insensitive Conversely, I CLOCK both the digital input waveform, f CLOCK DVDD. Figure 18 shows function of the ratio (f DVDD f ) for various update rates. In addition, Figure 19 ...
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R transformer’s impedance ratio and provides the proper source termination that results in a low VSWR. DIFFERENTIAL COUPLING USING AN OP AMP An op amp can also be used to perform a differential-to- single-ended conversion, ...
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AD9753 This is referred to as the Power Supply Rejection Ratio. For dc variations of the power supply, the resulting performance of the DAC directly corresponds to a gain error associated with the DAC’s full-scale current noise ...
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MARKER 1 [T1] RBW –74.34dBm VBW 9.71442886MHz SWT –30 1 [T1] –40 CH PWR ACP UP –50 ACP LOW –60 –70 1 –80 –90 –100 –110 C11 C11 –120 C0 C0 –130 START 100kHz 12.49MHz/ COMMENT A: 25 MSYMBOL, 64 ...
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AD9753 MARKER 1 [T2] RBW 10kHz –99.88dBm VBW 10kHz 859.91983968MHz SWT 2.8 s –20 1 [T2] –30 CH PWR ACP UP –40 ACP LOW 1 [T2] –50 2 [T2] – –70 –80 –90 1 –100 C11 C11 –110 ...
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EVALUATION BOARD The AD9753- evaluation board for the AD9753 TxDAC. Careful attention to layout and circuit design, combined with prototyping area, allows the user to easily and effectively evalu- ate the AD9753 in different modes of operation. Referring ...
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AD9753 RN2 VALUE RN1 1 VALUE 1B13 P1B13 1B12 P1B12 1B11 P1B11 1B10 P1B10 ...
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CLK+ 3 CLK– L1 DVDD FBEAD C13 10 F DGND 10V AVDD FBEAD J10 C14 10 F AGND 10V 1 J11 L3 CLKVDD FBEAD J12 C15 10 ...
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AD9753 Figure 36. Evaluation Board, Assembly—Top Figure 37. Evaluation Board, Assembly—Bottom –24– REV. B ...
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Figure 39. Evaluation Board, Layer 2, Ground Plane REV. B Figure 38. Evaluation Board, Top Layer –25– AD9753 ...
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AD9753 Figure 40. Evaluation Board, Layer 3, Power Plane Figure 41. Evaluation Board, Bottom Layer –26– REV. B ...
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ROTATED 90 CCW REV. B OUTLINE DIMENSIONS 48-Lead Low Profile Quad Flat Package [LQFP] (ST-48) Dimensions shown in millimeters 0.75 1.60 0.60 MAX 0.45 SEATING PLANE 10 6 0.20 2 0.09 VIEW A 7 3.5 ...
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AD9753 Revision History Location 9/03—Data Sheet changed from REV REV. B. Changes to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . ...