AD9889B/PCBZ Analog Devices Inc, AD9889B/PCBZ Datasheet - Page 7

• Manufacturer Part Number: AD9889B/PCBZ
• Description: Pb-free EVALUATION Kit AD9889B
• Manufacturer: Analog Devices Inc
• Series: Advantiv®r

Specifications of AD9889B/PCBZ

• Main Purpose: Video, Video Processing
• Embedded: No
• Utilized Ic / Part: AD9889B
• Primary Attributes: HDMI/DVI Transmitter
• Secondary Attributes: Color Space Converter, RGB, YCbCr, and DDR Compatible
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q5248134

Table 3. Pin Function Descriptions
BGA
D10, D9, C10,
C9, A10, B10,
A9, B9, A8, B8,
A7, B7, A6, B6,
A5, B5, A4, B4,
A3, B3, A2, B2,
A1, B1
D1
C2
C1
D2
J3
K3
E2
E1
F2, F1, G2, G1
H2
H1
J7
K1, K2
K10, J10
2
LFCSP
39 to 47,
50 to 63, 2
6
3
4
5
18
20
7
8
9 to 12
13
14
26
21, 22
30, 31
2
Pin No.
LQFP
50 to 58, 65 to
78, 2
6
3
4
5
23
25
7
8
9 to 12
13
14
33
27, 28
37, 38
2
Figure 4. 76-Ball BGA Configuration (Top View)
Mnemonic
D[23:0]
CLK
DE
HSYNC
VSYNC
EXT_SWG
HPD
S/PDIF
MCLK
I
SCLK
LRCLK
PD/A0
TxC−/TxC+
Tx2−/Tx2+
2
S[3:0]
10
9
Rev. A | Page 7 of 12
BOTTOM VIEW
8 7 6
(Not to Scale)
5 4
Type
I
I
I
I
I
I
I
I
I
I
I
I
I
O
O
3 2 1
1
Description
Video Data Input. Digital input in RGB or YCbCr format.
Supports CMOS logic levels from 1.8 V to 3.3 V.
Video Clock Input. Supports CMOS logic levels from 1.8 V
to 3.3 V.
Data Enable Bit for Digital Video. Supports CMOS logic levels
from 1.8 V to 3.3 V.
Horizontal Sync Input. Supports CMOS logic levels from
1.8 V to 3.3 V.
Vertical Sync Input. Supports CMOS logic levels from 1.8 V
to 3.3 V.
Sets Internal Reference Currents. Place 887 Ω resistor
(1% tolerance) between this pin and ground.
Hot Plug Detect Signal. This indicates to the interface
whether the receiver is connected. Supports 1.8 V to 5.0 V
CMOS logic levels.
S/PDIF (Sony/Philips Digital Interface) Audio Input. This is
the audio input from a Sony/Philips digital interface.
Supports CMOS logic levels from 1.8 V to 3.3 V.
Audio Reference Clock. 128 × N × f
Set to 128 × sampling frequency (f
512 × f
I
audio (two per input) available through I
logic levels from 1.8 V to 3.3 V.
I
Left/Right Channel Selection. Supports CMOS logic levels
from 1.8 V to 3.3 V.
Power-Down Control and I
address and the PD polarity are set by the PD/A0 pin state
when the supplies are applied to the AD9889B. Supports
1.8 V to 3.3 V CMOS logic levels.
Differential Clock Output. Differential clock output at pixel
clock rate; supports TMDS logic level.
Differential Output Channel 2. Differential output of the red
data at 10× the pixel clock rate; supports TMDS logic level.
2
2
S Audio Data Inputs. These represent the eight channels of
S Audio Clock. Supports CMOS logic levels from 1.8 V to 3.3 V.
A
B
C
D
E
F
G
H
J
K
S
. Supports 1.8 V to 3.3 V CMOS logic levels.
2
C Address Selection. The I
S
S
), 256 × f
with N = 1, 2, 3, or 4.
2
S. Supports CMOS
S
, 384 × f
AD9889B
S
2
, or
C