AD9961BCPZ Analog Devices Inc, AD9961BCPZ Datasheet - Page 27

• Manufacturer Part Number: AD9961BCPZ
• Description: Dual 16B, 200 MSPS D-A Converter
• Manufacturer: Analog Devices Inc

Specifications of AD9961BCPZ

• Features: *
• Package / Case: 72-VFQFN, CSP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name
Tx Scale 1
Rx Scale
Clock Doubler
Config
TX Clock Doubler
Config
RX Clock Doubler
Config
Clock Doubler
Config
Data Spectral
Inversion
Clock Doubler
Pulse Width
Register
Address
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
Bit(s)
7:5
4:0
7:5
4:0
7
6
5:4
3
2
1
0
7:4
3
2
1
7:4
3
2
1
7:0
7:4
3
2
1
0
7:6
5:3
2:0
Parameter
Unused
INT1_SCALE[4:0]
Unused
DEC_SCALE[4:0]
RXDLLRST
TXDLLRST
Unused
RXDLL_LKD
TXDLL_LKD
RXDBL_SEL
TXDBL_SEL
TX_UNLOCK[1:0]
TX_LOCK[1:0]
TX_DLYOFS[1:0]
TX_HYST[1:0]
RX_UNLOCK[1:0]
RX_LOCK[1:0]
RX_DLYOFS[1:0]
RX_HYST[1:0]
DBL_TAPDLY[7:0]
Unused
RX_INVQ
RX_INVI
TX_INVQ
TX_INVI
Unused
TX_DBLPW[2:0]
RX_DBLPW[2:0]
Rev. 0 | Page 27 of 60
Function
00000: multiply by 0.0.
00001: multiply by 0.0625.
…
11111: multiply by 1.9375.
Value of 1.4 multiplier applied to both I and Q channels just after
Interpolation Filter 1.
00000: multiply by 0.0.
00001: multiply by 0.0625.
11111: multiply by 1.9375.
Value of 3.2 multiplier applied to both I and Q channels just after the
decimation filter. The value of the gain applied is equal to DEC_SCALE/4.
00000: multiply by 0.0.
00001: multiply by 0.25.
11111: multiply by 7.75.
1: resets the Rx signal path clock doubler.
1: resets the Tx signal path clock doubler.
The Rx clock doubler is locked.
The Tx clock doubler is locked.
0: selects fixed pulse width clock doubler.
1: selects fixed duty cycle clock doubler.
See Table 22 for configuration recommendations.
0: selects fixed pulse width clock doubler.
1: selects fixed duty cycle clock doubler.
See Table 22 for configuration recommendations.
Sets the number of clock cycles for the unlock indicator. Set to 01.
Sets the number of clock cycles for the lock indicator. Set to 01.
Sets delay line offset of clock doubler. Set to 01.
Sets delay line hysteresis of clock doubler. Set to 01.
Sets the number of clock cycles for the unlock indicator. Set to 01.
Sets the number of clock cycles for the lock indicator. Set to 01.
Sets delay line offset of clock doubler. Set to 01.
Sets delay line hysteresis of clock doubler. Set to 01.
Sets the initial tap delay of the Rx and Tx clock doublers. Set to 0x02.
1: multiply Rxdata from QADC by −1.
1: multiply Rxdata from IADC by −1.
1: multiply Txdata for QDAC by −1.
1: multiply Txdata for IDAC by −1.
Sets the pulse width of the Tx clock doubler. See Table 22 for details.
Sets the pulse width of the Rx clock doubler. See Table 22 for details.
AD9961/AD9963