ADG728BRU Analog Devices Inc, ADG728BRU Datasheet - Page 4

• Manufacturer Part Number: ADG728BRU
• Description: Analog Switch / Multiplexer (Mux) IC
• Manufacturer: Analog Devices Inc
• Type: Analog Multiplexerr

Specifications of ADG728BRU

• No. Of Channels: 8
• Analog Switch Case Style: TSSOP
• No. Of Pins: 16
• Peak Reflow Compatible (260 C): No
• Leakage Current: 0.01nA
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• Rohs Status: RoHS non-compliant
• Function: Multiplexer/Demultiplexer
• Circuit: 1 x 8:1
• On-state Resistance: 4.5 Ohm
• Voltage Supply Source: Single Supply
• Voltage - Supply, Single/dual (±): 2.7 V ~ 5.5 V
• Current - Supply: 10µA
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-TSSOP (0.173", 4.40mm Width)
• Package: 16TSSOP
• Maximum On Resistance: 11@3V Ohm
• Maximum High Level Output Current: 120 mA
• Multiplexer Architecture: 8:1
• Maximum Turn-off Time: 115(Typ)@3V ns
• Maximum Turn-on Time: 130(Typ)@3V ns
• Power Supply Type: Single
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

TIMING CHARACTERISTICS
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
C
t
NOTES
1
2
3
4
Specifications subject to change without notice.
ADG728/ADG729
See Figure 1.
A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the V
C
Input filtering on both the SCL and SDA inputs suppress noise spikes which are less than 50 ns.
SCL
1
2
3
4
5
6
7
8
9
10
11
SP
the falling edge of SCL.
2
b
b
SDA
SCL
4
is the total capacitance of one bus line in pF. t
t
9
Limit at T
400
2.5
0.6
1.3
0.6
100
0.9
0
0.6
0.6
1.3
300
20 + 0.1C
250
300
0.1C
400
50
CONDITION
START
b
3
t
4
b
MIN
3
t
, T
3
MAX
R
and t
t
10
t
F
6
measured between 0.3 V
Unit
kHz max
ms min
ms min
ms min
ms min
ns min
ms max
ms min
ms min
ms min
ms min
ns max
ns min
ns max
ns max
ns min
pF max
ns max
1
CONDITION
(V
START
DD
t
2
= 2.7 V to 5.5 V. All specifications –40 C to +85 C, unless otherwise noted.)
t
11
DD
and 0.7 V
t
5
DD
Conditions/Comments
SCL Clock Frequency
SCL Cycle Time
t
t
t
t
t
t
t
t
a Start Condition
t
t
t
Capacitive Load for Each Bus Line
Pulsewidth of Spike Suppressed
IH
HIGH
LOW
HD, STA
SU, DAT
HD, DAT
SU, STA
SU, STO
BUF
R
F
F
.
, Rise Time of Both SCL and SDA when Receiving
, Fall Time of SDA when Receiving
, Fall Time of SDA when Transmitting
min of the SCL signal) in order to bridge the undefined region of
, Bus Free Time Between a STOP Condition and
, SCL Low Time
, SCL High Time
, Setup Time for Repeated Start
, Stop Condition Setup Time
, Start/Repeated Start Condition Hold Time
, Data Setup Time
CONDITION
REPEATED
, Data Hold Time
START
t
7
t
4
t
1
CONDITION
STOP
t
8