ADM8697ARWZ Analog Devices Inc, ADM8697ARWZ Datasheet - Page 6

• Manufacturer Part Number: ADM8697ARWZ
• Description: IMPROVED ADM697 I.C
• Manufacturer: Analog Devices Inc
• Type: Battery Backup Circuitr

Specifications of ADM8697ARWZ

• Number Of Voltages Monitored: 1
• Output: Push-Pull, Push-Pull
• Reset: Active High/Active Low
• Reset Timeout: 35 ms Minimum
• Voltage - Threshold: 1.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADM8696/ADM8697
The watchdog timeout period defaults to 1.6 s and the reset
pulse width defaults to 50 ms, but these times to be adjusted as
shown in Table I. Figure 4 shows the various oscillator configu-
rations that can be used to adjust the reset pulse width and
watchdog timeout period.
The internal oscillator is enabled when OSC SEL is high or
floating. In this mode, OSC IN selects between the 1.6 second
and 100 ms watchdog timeout periods. In either case, immedi-
ately after a reset the timeout period is 1.6 s. This gives the mi-
croprocessor time to reinitialize the system. If OSC IN is low,
the 100 ms watchdog period becomes effective after the first
transition of WDI. The software should be written such that the
I/O port driving WDI is left in its power-up reset state until the
initialization routines are completed and the microprocessor is
able to toggle WDI at the minimum watchdog timeout period of
70 ms.
OSC SEL
Low
Low
Floating or High
Floating or High
NOTE
With the OSC SEL pin low, OSC IN can be driven by an external clock signal, or an external capacitor can be connected between OSC IN and GND. The nominal
internal oscillator frequency is 10.24 kHz. The nominal oscillator frequency with external capacitor is: F
Figure 3. Watchdog Timeout Period and Reset Active Time
RESET
WDO
WDI
t
t
t
1
2
3
= WATCHDOG TIMEOUT PERIOD IMMEDIATELY FOLLOWING A RESET
= RESET TIME
= NORMAL (SHORT) WATCHDOG TIMEOUT PERIOD
0 TO 500kHz
CLOCK
t
1
Figure 4a. External Clock Source
t
2
Table I. ADM8696, ADM8697 Reset Pulse Width and Watchdog Timeout Selections
OSC IN
External Clock Input
External Capacitor
Low
Floating or High
t
1
7
8
OSC IN
OSC SEL
t
3
ADM869x
t
1
Normal
1024 CLKS
400 ms
100 ms
1.6 s
C/47 pF
Watchdog Timeout Period
–6–
Watchdog Output (WDO)
The Watchdog Output WDO provides a status output that goes
low if the watchdog timer “times out” and remains low until set
high by the next transition on the watchdog input. WDO is also
set high when LL
Figure 4d. Internal Oscillator (100 ms Watchdog)
Figure 4c. Internal Oscillator (1.6 s Watchdog)
Immediately After Reset
4096 CLKS
1.6 s
1.6 s
1.6 s
C
OSC
NC
NC
NC
OSC
Figure 4b. External Capacitor
C/47 pF
IN
(Hz) = 184,000/C (pF).
goes below the reset threshold.
8
7
8
7
7
8
OSC SEL
OSC IN
OSC IN
OSC SEL
OSC IN
OSC SEL
ADM869x
ADM869x
ADM869x
Reset Active Period
512 CLKS
200 ms
50 ms
50 ms
C/47 pF
REV. A