ADSP-21266SKSTZ-1D Analog Devices Inc, ADSP-21266SKSTZ-1D Datasheet - Page 37

• Manufacturer Part Number: ADSP-21266SKSTZ-1D
• Description: 150 MHz, 32Bit DSP Processor PB Free
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Fixed/Floating Pointr

Specifications of ADSP-21266SKSTZ-1D

• Interface: DAI, SPI
• Clock Rate: 150MHz
• Non-volatile Memory: ROM (512 kB)
• On-chip Ram: 256kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

OUTPUT DRIVE CURRENTS
Figure 29
ers of the ADSP-21266. The curves represent the current drive
capability of the output drivers as a function of output voltage.
TEST CONDITIONS
The ac signal specifications (timing parameters) appear in
Table 13 on Page 19
output disable time, output enable time, and capacitive loading.
Timing is measured on signals when they cross the 1.5 V level as
described in
sured between the point that the first signal reaches 1.5 V and
the point that the second signal reaches 1.5 V.
–20
–30
–40
–10
Figure 30. Equivalent Device Loading for AC Measurements
40
30
20
10
OUTPUT 1.5V
Figure 31. Voltage Reference Levels for AC Measurements
0
OUTPUT
0
shows typical I-V characteristics for the output driv-
INPUT
Figure
OR
PIN
TO
V OL
0.5
31. All delays (in nanoseconds) are mea-
3.47V, –45°C
SWEEP (V DDEXT ) VOLTAGE (V)
through
Figure 29. Typical Drive
1
(Includes All Fixtures)
3.11V, 125°C
1.5
Table 34 on Page
30pF
V OH
2
3.11V, 125°C
2.5
50
3.3V, 25°C
3
36. These include
3.3V, 25°C
3.47V, –45°C
Rev. C | Page 37 of 44 | October 2007
3.5
1.5V
1.5V
CAPACITIVE LOADING
Output delays and holds are based on standard capacitive loads:
30 pF on all pins (see
how output delays and holds vary with load capacitance (note
that this graph or derating does not apply to output disable
delays). The graphs of
not be linear outside the ranges shown for Typical Output Delay
vs. Load Capacitance and Typical Output Rise Time (20%–80%,
V = Min) vs. Load Capacitance.
12
10
0
8
6
4
2
12
10
8
6
4
2
0
0
0
Figure 33. Typical Output Rise/Fall Time
Figure 32. Typical Output Rise Time
y = 0.0467x + 1.6323
50
y = 0.049x + 1.5105
50
Figure
(20%–80%, V
(20%–80%, V
Figure
LOAD CAPACITANCE (pF)
LOAD CAPACITANCE (pF)
30).
100
32,
100
y = 0.0482x + 1.4604
y = 0.045x + 1.524
DDEXT
Figure 33
DDEXT
Figure
= Max)
= Min)
RISE
150
150
33, and
RISE
ADSP-21266
shows graphically
FALL
FALL
Figure 34
200
200
250
may
250