ADSP-2188MBSTZ-266 Analog Devices Inc, ADSP-2188MBSTZ-266 Datasheet - Page 25

56k/48k, 16-bit DSP, 75 MIPS

ADSP-2188MBSTZ-266

Manufacturer Part Number
ADSP-2188MBSTZ-266
Description
56k/48k, 16-bit DSP, 75 MIPS
Manufacturer
Analog Devices Inc
Series
ADSP-21xxr
Type
Fixed Pointr
Datasheet

Specifications of ADSP-2188MBSTZ-266

Interface
Host Interface, Serial Port
Clock Rate
66MHz
Non-volatile Memory
External
On-chip Ram
256kB
Voltage - I/o
3.30V
Voltage - Core
2.50V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-LQFP
Device Core Size
16b
Architecture
Enhanced Harvard
Format
Fixed Point
Clock Freq (max)
66MHz
Mips
66
Device Input Clock Speed
66MHz
Ram Size
256KB
Operating Supply Voltage (typ)
2.5/3.3V
Operating Supply Voltage (min)
2.25V
Operating Supply Voltage (max)
2.75/3.6V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
100
Package Type
LQFP
Package
100LQFP
Numeric And Arithmetic Format
Fixed-Point
Maximum Speed
66 MHz
Device Million Instructions Per Second
66 MIPS
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADSP-2188MBSTZ-266
Quantity:
3 000
Part Number:
ADSP-2188MBSTZ-266
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Parameter
Interrupts and Flags
Timing Requirements:
t
t
Switching Characteristics:
t
t
NOTES
1
2
3
4
5
If IRQx and FI inputs meet t
Edge-sensitive interrupts require pulsewidths greater than 10 ns; level-sensitive interrupts must be held low until serviced.
IRQx = IRQ0, IRQ1, IRQ2, IRQL0, IRQL1, IRQLE.
PFx = PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7.
Flag Outputs = PFx, FL0, FL1, FL2, FO.
IFS
IFH
FOH
FOD
the following cycle. (Refer to “Interrupt Controller Operation” in the Program Control chapter of the ADSP-2100 Family User’s Manual for further information on
interrupt servicing.)
IRQx, FI, or PFx Setup before CLKOUT Low
IRQx, FI, or PFx Hold after CLKOUT High
Flag Output Hold after CLKOUT Low
Flag Output Delay from CLKOUT Low
IFS
and t
IFH
setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on
OUTPUTS
CLKOUT
FLAG
IRQx
PFx
FI
5
5
t
FOH
t
FOD
1, 2, 3, 4
1, 2, 3, 4
t
IFH
t
IFS
Min
0.25t
0.25t
0.5t
CK
CK
CK
– 5
+ 10
ADSP-2188M
Max
0.5t
CK
+ 4
Unit
ns
ns
ns
ns

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