ADUC7061BCPZ32-RL Analog Devices Inc, ADUC7061BCPZ32-RL Datasheet - Page 71

• Manufacturer Part Number: ADUC7061BCPZ32-RL
• Description: DUAL 24-BIT AFE AND ARM 7 I.C
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7061BCPZ32-RL

• Design Resources: USB Based Temperature Monitor Using ADuC7061 and an External RTD (CN0075) 4 mA-to-20 mA Loop-Powered Temperature Monitor Using ADuC7060/1 (CN0145)
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 10MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 8
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 2.625 V
• Data Converters: A/D 5x24b, 8x24b, D/A 1x14b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 32-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Timer2 Control Register
Name:
Address:
Default value:
Access:
Function:
Table 81. T2CON MMR Bit Designations
Bit
15:9
8
7
6
5
4
3:2
1
0
Name
T2DIR
T2EN
T2MOD
WDOGMDEN
T2SCALE
WDOGENI
T2PDOFF
T2CON
0xFFFF0368
0x0000
Read and write
This 16-bit MMR configures the mode of operation of Timer2, as described in detail in Table 81.
Description
Reserved. These bits are reserved and should be written as 0 by user code.
Count up/count down enable.
Set by user code to configure Timer2 to count up.
Cleared by user code to configure Timer2 to count down.
Timer2 enable.
Set by user code to enable Timer2.
Cleared by user code to disable Timer2.
Timer2 operating mode.
Set by user code to configure Timer2 to operate in periodic mode.
Cleared by user to configure Timer2 to operate in free running mode.
Watchdog timer mode enable.
Set by user code to enable watchdog mode.
Cleared by user code to disable watchdog mode.
Reserved. This bit is reserved and should be written as 0 by user code.
Timer2 clock (32.768 kHz) prescaler.
00 = 32.768 kHz (default).
01 = source clock/16.
10 = source clock/256.
11 = reserved.
Watchdog timer IRQ enable.
Set by user code to produce an IRQ instead of a reset when the watchdog reaches 0.
Cleared by user code to disable the IRQ option.
Stop Timer2 when power-down is enabled.
Set by user code to stop Timer2 when the peripherals are powered down using Bit 4 in the POWCON0 MMR.
Cleared by user code to enable Timer2 when the peripherals are powered down using Bit 4 in the
POWCON0 MMR.
Rev. B | Page 71 of 108
ADuC7060/ADuC7061