ADUM1311ARWZ-RL Analog Devices Inc, ADUM1311ARWZ-RL Datasheet - Page 6

• Manufacturer Part Number: ADUM1311ARWZ-RL
• Description: IC,Digital Coupler,HYBRID,SOP,16PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: iCoupler®r

Specifications of ADUM1311ARWZ-RL

• Inputs - Side 1/side 2: 2/1
• Number Of Channels: 3
• Isolation Rating: 2500Vrms
• Voltage - Supply: 2.7 V ~ 5.5 V
• Data Rate: 1Mbps
• Propagation Delay: 100ns
• Output Type: Logic
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Operating Temperature: -40°C ~ 105°C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 105C
• Package Type: SOIC W
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuM1310/ADuM1311
Parameter
1
2
3
4
5
6
7
8
9
10
The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section.
See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through
Figure 12 for total V
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
t
measured from the 50% level of the rising edge of the V
t
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
CM
Input enable time is the duration from when V
transitions. If an input data logic transition within a given channel does occur within this time interval, the output of that channel reaches the correct state within the
much shorter duration, as determined by the propagation delay specifications within this data sheet. Input disable time is the duration from when V
until the output states are guaranteed to reach their programmed output levels, as determined by the CTRL
I
the same orientation as Channel A must be included to account for the total current consumed.
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
within the recommended operating conditions.
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
that can be sustained while maintaining V
magnitude is the range over which the common mode is slewed.
DDx (Q)
PHL
PSK
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 6 through Figure 8 for information
For All Models
H
propagation delay is measured from the 50% level of the falling edge of the V
is the magnitude of the worst-case difference in t
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient Immunity
Common-Mode Transient Immunity
Refresh Rate
Input Enable Time
Input Disable Time
Input Supply Current per Channel,
Output Supply Current per Channel,
Input Dynamic Supply Current
Output Dynamic Supply Current
is the maximum common-mode voltage slew rate that can be sustained while maintaining V
is the quiescent current drawn from the corresponding supply by a single channel. To calculate the total quiescent current, an additional inaccessible channel in
at Logic High Output
at Logic Low Output
Quiescent
Quiescent
per Channel
per Channel
DD1
9
9
10
10
and V
8
8
DD2
supply currents as a function of data rate for ADuM1310/ADuM1311 channel configurations.
7
7
O
< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
DISABLE
Symbol
t
|CM
|CM
f
t
t
I
I
I
I
DDI (Q)
DDO (Q)
DDI (D)
DDO (D)
is set low until the output states are guaranteed to match the input states in the absence of any input data logic
r
R
ENABLE
DISABLE
PHL
/t
F
or t
Ix
H
L
|
|
signal to the 50% level of the rising edge of the V
PLH
that is measured between units at the same operating temperature, supply voltages, and output load
Min
25
25
Rev. G | Page 6 of 24
Ix
signal to the 50% level of the falling edge of the V
Typ
2.5
35
35
1.1
2.0
5.0
0.25
0.19
0.07
0.02
O
> 0.8 V
DD2
Ox
Max
0.38
0.33
2
. CM
signal.
logic state (see Table 13).
L
is the maximum common-mode voltage slew rate
Unit
ns
kV/μs
kV/μs
Mbps
μs
μs
mA
mA
mA/
Mbps
mA/
Mbps
Test Conditions
C
V
transient magnitude = 800 V
V
transient magnitude = 800 V
V
V
L
Ix
Ix
IA
IA
= 15 pF, CMOS signal levels
, V
, V
= V
= 0 V, V
Ox
IB
IB
, V
, V
DD1
signal. t
IC
IC
or V
CM
= 0 V or V
= 0 V or V
= 1000 V,
DD2
PLH
propagation delay is
, V
DISABLE
CM
DD1
DD1
= 1000 V,
is set high