ADV212BBCZ-115 Analog Devices Inc, ADV212BBCZ-115 Datasheet
ADV212BBCZ-115
Specifications of ADV212BBCZ-115
Available stocks
Related parts for ADV212BBCZ-115
ADV212BBCZ-115 Summary of contents
Page 1
FEATURES Implementation of a JPEG2000-compatible video CODEC for video and still images through the ADV212 Wavescale video compression/decompression engine Identical pinout and footprint to the ADV202; and support for all the functionality of the ADV202 Power reduction of at least ...
Page 2
ADV212 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 JPEG2000 Feature Support .............................................................. 3 Functional Block Diagram .............................................................. 3 Specifications ..................................................................................... 4 Supply Voltages and Current ...................................................... 4 Input/Output Specifications ........................................................ ...
Page 3
The ADV212 can process images at a rate of 40 MSPS in reversible mode and at higher rates when used in irreversible mode. The ADV212 contains a dedicated wavelet transform engine, three entropy CODECs, an on-board memory system, and an ...
Page 4
ADV212 SPECIFICATIONS Specifications apply to IOVDD = 2 3.3 V over the operating temperature range, unless otherwise specified. SUPPLY VOLTAGES AND CURRENT Table 1. Parameter DC Supply Voltage, Core DC Supply Voltage, Input/Output Input Range Operating Ambient Temperature ...
Page 5
CLOCK AND RESET SPECIFICATIONS Table 3. Parameter MCLK Period MCLK Frequency MCLK Width Low MCLK Width High VCLK Period VCLK Frequency VCLK Width Low VCLK Width High RESET Width Low For a definition of MCLK, see Figure 32. 1 MCLK ...
Page 6
ADV212 NORMAL HOST MODE—WRITE OPERATION Table 4. Parameter WE to ACK, Direct Registers and FIFO Accesses WE to ACK, Indirect Registers Data Setup Data Hold Address Setup Address Hold Setup CS Hold Write Inactive Pulse Width (Minimum ...
Page 7
NORMAL HOST MODE—READ OPERATION Table 5. Parameter RD to ACK, Direct Registers and FIFO Accesses RD to ACK, Indirect Registers Read Access Time, Direct Registers Read Access Time, Indirect Registers Data Hold Setup Address Setup CS Hold ...
Page 8
ADV212 DREQ/DACK DMA MODE—SINGLE FIFO WRITE OPERATION Table 6. Parameter DREQ Pulse Width DACK Assert to Subsequent DREQ Delay WE to DACK Setup Data to DACK Deassert Setup Data to DACK Deassert Hold DACK Assert Pulse Width DACK Deassert Pulse ...
Page 9
DREQ PULSE t DREQ DREQ DACK DACK LOW DACK WEFB HDATA Figure 7. Single Write Cycle for Fly-By DMA Mode ( DREQ Pulse Width Is Programmable) FCS0 RD FIFO NOT FULL FSRQ0 ...
Page 10
ADV212 DREQ/DACK DMA MODE—SINGLE FIFO READ OPERATION Table 7. Parameter DREQ Pulse Width DACK Assert to Subsequent DREQ Delay RD to DACK Setup DACK to Data Valid Data Hold DACK Assert Pulse Width DACK Deassert Pulse Width RD Hold after ...
Page 11
DREQ PULSE t DREQ DREQ DACK DACK LOW DACK RDFB t RD HDATA 0 Figure 11. Single Read Cycle for Fly-By DMA Mode ( DREQ Pulse Width Is Programmable) FCS0 RD FIFO NOT EMPTY FSRQ0 t t ...
Page 12
ADV212 EXTERNAL DMA MODE—FIFO WRITE, BURST MODE Table 8. Parameter DREQ Pulse Width DREQ Deassert (DR × PULS = 0) DACK to WE Setup Data Setup Data Hold WE Assert Pulse Width WE Deassert Pulse Width WE ...
Page 13
EXTERNAL DMA MODE—FIFO READ, BURST MODE Table 9. Parameter DREQ Pulse Width DREQ Deassert (DR × PULS = 0) DACK to RD Setup RD to Data Valid Data Hold RD Assert Pulse Width RD Deassert Pulse Width ...
Page 14
ADV212 STREAMING MODE (JDATA)—FIFO READ/WRITE Table 10. Parameter MCLK to JDATA Valid MCLK to VALID Assert/Deassert HOLD Setup to Rising MCLK HOLD Hold from Rising MCLK JDATA Setup to Rising MCLK JDATA Hold from Rising MCLK 1 For a definition ...
Page 15
VDATA MODE TIMING Table 11. Parameter VCLK to VDATA Valid Delay (VDATA Output) VDATA Setup to Rising VCLK (VDATA Input) VDATA Hold from Rising VCLK (VDATA Input) HSYNC Setup to Rising VCLK HSYNC Hold from Rising VCLK VCLK to HSYNC ...
Page 16
ADV212 VCLK VDATA TD VDATA (OUT) HSYNC (IN) VSYNC (IN) FIELD (IN) VCLK VDATA TD VDATA (OUT) HSYNC (IN) VSYNC (IN) FIELD (IN) VCLK VDATA (OUT) HSYNC (OUT) VSYNC (OUT) FIELD TD FIELD (OUT) Figure 26. Decode Video Mode Timing—CCIR ...
Page 17
RAW PIXEL MODE TIMING Table 12. Parameter VCLK to PIXELDATA Valid Delay (PIXELDATA Output) PIXELDATA Setup to Rising VCLK (PIXELDATA Input) PIXELDATA Hold from Rising VCLK (PIXELDATA Input) VCLK to VRDY Valid Delay VFRM Setup to Rising VCLK (VFRAME Input) ...
Page 18
ADV212 JTAG TIMING Table 13. Parameter TCK Period TDI or TMS Setup Time TDI or TMS Hold Time TDO Hold Time TDO Valid TRS Hold Time TRS Setup Time TRS Pulse Width Low TCK TDO TDI TMS TRS Mnemonic Min ...
Page 19
... THERMAL RESISTANCE θ is specified for the worst-case conditions, that is, a device JA soldered in a circuit board for surface-mount packages. Table 15. Thermal Resistance Package Type 144-Ball ADV212BBCZ 121-Ball ADV212BBCZ ESD CAUTION Rev Page ADV212 θ θ Unit JA JC 22.5 3.8 ° ...
Page 20
ADV212 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS BOTTOM VIEW (Not to Scale) Figure 30.121-Ball Pin Configuration Table 16. Pin Function Descriptions 121-Ball Package 144-Ball Package Pin No. Location Pin No. ...
Page 21
Package 144-Ball Package Pin No. Location Pin No G10 Pins Location Mnemonic Used G11 ACK 1 G10 IRQ 1 F12 1 DREQ0 FSRQ0 VALID CFG1 F11 DACK0 1 ...
Page 22
ADV212 121-Ball Package 144-Ball Package Pin No. Location Pin No. 65 F10 92 J4, H1 111 81 H4, G4 100 ...
Page 23
Package 144-Ball Package Pin No. Location Pin No. 101 K2 122 115 L5 123 103 K4 109 102 K3 110 44, 43, 29, D11, D10 48, 31, 32, 18 C7, C9, C10 ...
Page 24
ADV212 121-Ball Package 144-Ball Package Pin No. Location Pin No 9,11, A1, A4, A9 12, 23, 33, 39, A11, C1, 17, 20, 29, 45 C11, D6, E1, 32, 41, 44, 51, 55, ...
Page 25
THEORY OF OPERATION The input video or pixel data is passed to the ADV212 pixel interface, and samples are deinterleaved and passed to the wavelet engine, which decomposes each tile or frame into subbands using the 5/3 or 9/7 filters. ...
Page 26
ADV212 ADV212 INTERFACES There are several possible ways to interface to the ADV212 using the VDATA bus and the HDATA bus or the HDATA bus alone. VIDEO INTERFACE (VDATA BUS) The video interface can be used in applications in which ...
Page 27
CONTROL ACCESS REGISTERS With the exception of the indirect address and data registers (IADDR and IDATA), all control/status registers in the ADV212 are 16 bits wide and are half-word (16-bit) addressable only. When 32-bit host mode is enabled, the upper ...
Page 28
ADV212 INTERNAL REGISTERS This section describes the internal registers of the ADV212. DIRECT REGISTERS The ADV212 has 16 direct registers, as listed in Table 18. Table 18. Direct Registers Address Name 0x00 Pixel 0x01 Code 0x02 ATTR 0x03 Reserved 0x04 ...
Page 29
INDIRECT REGISTERS In certain modes, such as custom-specific input format or HIPI mode, indirect registers must be accessed by the user through the IADDR and IDATA registers. The indirect register address space starts at Internal Address 0xFFFF0000. Table 19. Indirect ...
Page 30
ADV212 PLL REGISTERS The ADV212 uses the PLL_HI and PLL_LO direct registers to configure the PLL. Any time the PLL_LO register is modified, the host must wait at least 20 µs before reading from or writing to another register. If ...
Page 31
HARDWARE BOOT MODES AND POWER CONSIDERATIONS The boot mode can be configured via hardware using the CFG pins or via software. The first boot mode after power-up is set by the CFG pins and should always be as described in ...
Page 32
ADV212 VIDEO INPUT FORMATS The ADV212 supports a wide variety of formats for uncom- pressed video and still image data. The actual interface and bus modes selected for transferring uncompressed data dictates the allowed size of the input data and ...
Page 33
Table 24. Maximum Supported Tile Width for Data Input on HDATA and VDATA Buses Compression Mode 9/7i 9/7i 9/7i 5/3i 5/3i 5/3i 5/3r 5/3r 5/3r Input Format Single-component Two-component Three-component Single-component Two-component Three-component Single-component Two-component Three-component Rev Page ...
Page 34
ADV212 APPLICATIONS INFORMATION This section describes typical video applications for the ADV212 JPEG2000 video processor. ENCODE—MULTICHIP MODE Due to the data input rate limitation (see Table 22), an 1080i application requires at least two ADV212s to encode or decode full-resolution ...
Page 35
DECODE—MULTICHIP MASTER/SLAVE In a master/slave configuration expected that the master HVF outputs are connected to the slave HVF inputs and that each SCOMM5 pin is connected to the same GPIO on the host. 32-BIT HOST CPU DATA[31:0] ADDR[3:0] ...
Page 36
ADV212 DIGITAL STILL CAMERA/CAMCORDER Figure typical configuration for a digital camera or camcorder. AD9843A 10 D[9:0] SDATA SCK SL Figure 35. Digital Still Camera/Camcorder Encode Application for 10-Bit Pixel Data Using Raw Pixel Mode ADV212 FPGA MCLK ...
Page 37
ENCODE/DECODE SDTV VIDEO APPLICATION Figure 36 shows two ADV212 chips using a 10-bit CCIR 656 in normal host mode. ENCODE MODE 32-BIT HOST CPU DATA[31:0] ADDR[3:0] DECODE MODE 32-BIT HOST CPU DATA[31:0] ADDR[3:0] ADV212 VDATA[11:2] VCLK HDATA[31:0] 27MHz MCLK INTR ...
Page 38
ADV212 32-BIT HOST APPLICATION Figure 37 shows two ADV212 chips using a 10-bit CCIR 656 in normal host mode. FPGA DATA[31:0] 32-BIT HOST CPU DATA[31:0] ADDR[3:0] FPGA DATA[31:0] 31-BIT HOST CPU DATA[31:0] ADDR[3:0] ADV212 DREQ0 DREQ0 DACK0 DACK0 VDATA[11:2] HDATA[31:0] ...
Page 39
HIPI (HOST INTERFACE—PIXEL INTERFACE) Figure typical configuration using HIPI mode. 32-BIT HOST Y0/G0<MSB> HDATA<31> Y0/G0<6> HDATA<30> Y0/G0<5> HDATA<29> Y0/G0<4> HDATA<28> Y0/G0<3> HDATA<27> Y0/G0<2> HDATA<26> Y0/G0<1> HDATA<25> Y0/G0<0> HDATA<24> Cb0/G1<MSB> HDATA<23> Cb0/G1<6> HDATA<22> Cb0/G1<5> HDATA<21> Cb0/G1<4> HDATA<20> Cb0/G1<3> ...
Page 40
ADV212 JDATA INTERFACE Figure 39 shows a typical configuration using JDATA with a dedicated JDATA output, 16-bit host, and 10-bit CCIR 656. FPGA 16-BIT HOST CPU DATA[15:0] ADDR[3:0] ADV212 YCrCb JDATA[7:0] VDATA[11:2] HOLD FIELD VALID VSYNC HSYNC VCLK HDATA[15:0] IRQ ...
Page 41
OUTLINE DIMENSIONS DETAIL A * 1.85 1.71 1.40 * 1.85 MAX 12.20 12. 11.80 BALL A1 CORNER 10.00 BSC SQ 1.00 BSC BOTTOM VIEW TOP VIEW DETAIL A 0.50 NOM 0.30 MIN 0.70 ...
Page 42
... ADV212 ORDERING GUIDE Temperature Model 1 Range ADV212BBCZ-115 −40°C to +85°C ADV212BBCZRL-115 −40°C to +85°C ADV212BBCZ-150 −40°C to +85°C ADV212BBCZRL-150 −40°C to +85° RoHS Compliant Part. Speed Grade Operating Voltage Package Description 115 MHz 1.5 V Internal, 121-Ball Chip Scale Package Ball Grid Array [CSP_BGA] 2 ...
Page 43
NOTES Rev Page ADV212 ...
Page 44
ADV212 NOTES ©2006–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06389-0-4/10(B) Rev Page ...