ADV3201ASWZ Analog Devices Inc, ADV3201ASWZ Datasheet
ADV3201ASWZ
Specifications of ADV3201ASWZ
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ADV3201ASWZ Summary of contents
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FEATURES Large, 32 × 32, nonblocking switch array (ADV3200 (ADV3201) operation Pin-compatible 32 × 16 versions available (ADV3202/ADV3203) Single 5 V supply, dual ±2.5 V supply, or dual ±3.3 V supply (G = ...
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ADV3200/ADV3201 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 OSD Disabled ................................................................................ 3 OSD Enabled ................................................................................. 4 Timing Characteristics (Serial Mode) ....................................... 5 ...
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SPECIFICATIONS OSD DISABLED V = ±2.5 V (ADV3200 ±3.3 V (ADV3201 unless otherwise noted. Table 1. Parameter Test Conditions/Comments DYNAMIC PERFORMANCE −3 dB Bandwidth 200 mV p p-p Gain Flatness 0.1 dB, ...
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ADV3200/ADV3201 Parameter Test Conditions/Comments Input Capacitance Input Resistance Input Bias Current Sync-tip clamp enabled Sync-tip clamp enabled Sync-tip clamp disabled SWITCHING CHARACTERISTICS Enable On Time 50% update to 1% settling Switching Time Step 50% ...
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Parameter OSD DC PERFORMANCE Gain Error ADV3200 ADV3201 OSD INPUT CHARACTERISTICS Input Offset Voltage Input Bias Current OSD SWITCHING CHARACTERISTICS OSD Switch Delay Step OSD Switching Transient (Glitch) ADV3200 ADV3201 TIMING CHARACTERISTICS (SERIAL MODE) Table 3. Parameter Serial ...
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ADV3200/ADV3201 CLK DATA IN UPDATE Table 4. Logic Levels, DVCC = 3 RESET, CS, RESET, CS, ...
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ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Rating Analog Supply Voltage 7.5 V (VPOS − VNEG) Digital Supply Voltage 6 V (DVCC − DGND) Ground Potential Difference +0 −4 V (VNEG − DGND) Maximum Potential Difference DVCC − VNEG ...
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ADV3200/ADV3201 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DVCC 1 PIN 1 OSD00 2 3 RESET CLK 4 DATA IN 5 DATA OUT 6 UPDATE OSDS15 9 IN00 10 OSDS14 11 IN01 12 OSDS13 13 IN02 14 OSDS12 15 ...
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Table 7. Pin Function Descriptions Pin Mnemonic Description 1 DVCC Digital Positive Power Supply. 2 OSD00 OSD Input Number 0. 3 RESET Control Pin: First and Second Rank Reset. 4 CLK Control Pin: Serial Data Clock. 5 DATA IN Control ...
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ADV3200/ADV3201 Pin Mnemonic Description 101 IN28 Input Number 28. 102 OSDS28 Control Pin: OSD Select Number 28. 103 IN27 Input Number 27. 104 OSDS27 Control Pin: OSD Select Number 27. 105 IN26 Input Number 26. 106 OSDS26 Control Pin: OSD ...
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TRUTH TABLE AND LOGIC DIAGRAM Table 8. Operation Truth Table CS UPDATE CLK DATA Data don’t care. 2 Data ...
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ADV3200/ADV3201 I/O SCHEMATICS 4kΩ (ADV3201 ONLY) VREF Figure 7. Enabled Output (See Also Figure 16) 4kΩ 3.7pF (ADV3201 ONLY) VREF Figure 8. Disabled Output (See Also Figure 16) IN VNEG Figure 9. Receiver (See Also Figure 16) IN 5µA VNEG ...
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TYPICAL PERFORMANCE CHARACTERISTICS ADV3200 V = ±2 25° 150 Ω –2 OSDxx –4 –6 –8 –10 – FREQUENCY (MHz) Figure 17. ADV3200 Small Signal Frequency Response, 200 ...
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ADV3200/ADV3201 600 500 400 300 200 100 0 354 362 370 378 FREQUENCY (MHz) Figure 23. ADV3200 −3 dB Bandwidth Histogram, One Device, All 1024 Channels 500 475 450 425 400 375 350 325 300 NUMBER OF ENABLED CHANNELS Figure ...
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FREQUENCY (MHz) Figure 29. ADV3200 Crosstalk, All Hostile, RTO 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 1M 10M 100M FREQUENCY (Hz) Figure ...
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ADV3200/ADV3201 1.2 0.8 0.4 0 –0.4 –0.8 –1 TIME (ns) Figure 35. ADV3200 Large Signal Pulse Response p-p 2 UPDATE –1 V – TIME ...
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INPUT DC OFFSET (V) Figure 41. ADV3200 Differential Gain, Carrier Frequency = 3.58 MHz, Subcarrier Amplitude = 300 mV p-p 0.010 0.005 0 –0.005 ...
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ADV3200/ADV3201 250 200 150 100 50 0 OFFSET (mV) Figure 47. ADV3200 Input Offset Distribution, One Device, All 1024 Channels 1.5 UPDATE 1.0 0.5 0 –0.5 –1.0 –1 TIME (ns) Figure 48. ADV3200 Enable Time 70 ...
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TIME (ns) Figure 53. ADV3200 Large Signal Pulse with Capacitive Loads p-p 1.5 5pF 10pF 1.0 2pF 0pF 0.5 0 ...
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ADV3200/ADV3201 ADV3201 V = ±3 25° 150 Ω –2 –4 – FREQUENCY (MHz) Figure 56. ADV3201 Small Signal Frequency Response, 200 mV p-p 8 ...
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FREQUENCY (MHz) Figure 62. ADV3201 −3 dB Bandwidth Histogram, One Device, All 1024 Channels 350 340 330 320 310 300 NUMBER OF ENABLED CHANNELS Figure ...
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ADV3200/ADV3201 0 –20 –40 –60 –80 –100 –120 1 10 FREQUENCY (MHz) Figure 68. ADV3201 Crosstalk, All Hostile, RTO 0 –20 –40 –60 –80 –100 –120 1M 10M FREQUENCY (Hz) Figure 69. ADV3201 Off Isolation, RTO 1M 100k 10k 1k ...
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INxx –1 TIME (ns) Figure 74. ADV3201 Large Signal Pulse Response p-p 2 UPDATE V RISING EDGE OUT FALLING EDGE OUT ...
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ADV3200/ADV3201 0.10 0.05 0 –0.05 –0.10 –0.15 –0.7 –0.5 –0.3 –0.1 0.1 INPUT DC OFFSET (V) Figure 80. ADV3201 Differential Gain, Carrier Frequency = 3.58 MHz, Subcarrier Amplitude = 300 mV p-p 0.05 0.04 0.03 0.02 0.01 0 –0.01 –0.02 ...
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OFFSET (mV) Figure 86. ADV3201 Input Offset Distribution, One Device, All 1024 Channels 1.5 UPDATE 1.0 0.5 0 –0.5 –1.0 –1 TIME (ns) Figure 87. ADV3201 Enable Time ...
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ADV3200/ADV3201 1.5 5pF 10pF 1.0 2pF 0pF 0.5 0 –0.5 –1.0 –1 TIME (ns) Figure 92. ADV3201 Large Signal Pulse with Capacitive Loads p-p 1.5 5pF 10pF 1.0 2pF 0pF 0.5 ...
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THEORY OF OPERATION The ADV3200/ADV3201 are single-ended crosspoint arrays with 32 outputs, each of which can be connected to any one of 32 inputs. Thirty-two switchable input stages are connected to each output buffer to form 32-to-1 multiplexers. There are ...
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ADV3200/ADV3201 In addition to a receiver, each input also has a sync-tip clamp for use in ac-coupled applications. All clamps are enabled or disabled according to the first serial data bit shifted in during programming logic. When enabled, the clamp ...
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APPLICATIONS INFORMATION PROGRAMMING The ADV3200/ADV3201 are programmed serially through a 193-bit serial word that updates the matrix and the state of the sync-tip clamps each time the part is programmed. Serial Programming Description The serial programming mode uses the CLK, ...
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ADV3200/ADV3201 Sync-Tip Clamp for AC-Coupled Inputs The ADV3200/ADV3201 sync-tip clamp, when enabled, clamps the most negative voltage of the video to equal VCLAMP. This provides the correct dc level to the crosspoint switch and ensures that, regardless of average picture ...
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ON-SCREEN DISPLAY (OSD) The ADV3200/ADV3201 features dedicated 2:1 muxes for each of the 32 outputs that allow external video or dc levels to be inserted and switched in with the regular input channel. The OSD mux switches in 20 ns, ...
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ADV3200/ADV3201 VPOS I OUTPUT, QUIESCENT QNPN V QPNP I I OUTPUT, QUIESCENT VNEG Figure 105. Simplified Output Stage Example For the ADV3200 ambient temperature of 85°C, with all 32 outputs driving 1 V rms into 150 Ω loads ...
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Measuring Crosstalk Crosstalk is measured by applying a signal to one or more channels and measuring the relative strength of that signal on a desired selected channel. The measurement is usually expressed as decibels below the magnitude of the test ...
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ADV3200/ADV3201 Effect of Impedances on Crosstalk Input side crosstalk can be influenced by the output impedance of the sources that drive the inputs. The lower the impedance of the drive source, the lower the magnitude of the crosstalk. The dominant ...
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ADV3200/ ADV3201 INxx 75Ω Figure 106. Fly-By Input Termination (Grounds for the Two Transmission Lines Must Be Tied Together Close to the INxx Pin) If multiple ADV3200/ADV3201s are to be driven in parallel, a fly-by input termination scheme is very ...
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... VIEW A ROTATED 90° CCW ORDERING GUIDE Model Temperature Range 1 ADV3200ASWZ −40°C to +85°C ADV3201ASWZ 1 −40°C to +85° RoHS Compliant Part. ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07176-0-10/08(0) 26.20 26 ...