AM29LV800BB-90EC AMD (ADVANCED MICRO DEVICES), AM29LV800BB-90EC Datasheet - Page 26

• Manufacturer Part Number: AM29LV800BB-90EC
• Description: Flash Memory IC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM29LV800BB-90EC

• Memory Configuration: 1M X 8 / 512k X 16 Bit
• Memory Size: 8Mbit
• Package/case: 48-TSOP
• Supply Voltage Max: 3.6V
• Access Time, Tacc: 90nS
• Mounting Type: Surface Mount
• Supply Voltage: 3V

24
Notes:
1. Read toggle bit twice to determine whether or not it is
2. Recheck toggle bit because it may stop toggling as DQ5
toggling. See text.
changes to “1”. See text.
No
Figure 6. Toggle Bit Algorithm
Complete, Write
Reset Command
Read DQ7–DQ0
Read DQ7–DQ0
Read DQ7–DQ0
Program/Erase
Operation Not
Toggle Bit
Toggle Bit
DQ5 = 1?
= Toggle?
= Toggle?
START
Twice
Yes
Yes
Yes
(Notes
1, 2)
(Note
Operation Complete
No
No
Program/Erase
Am29LV800B
The DQ5 failure condition may appear if the system
tries to program a “1” to a location that is previously
programmed to “0.” Only an erase operation can
change a “0” back to a “1.” Under this condition,
the device halts the operation, and when the opera-
tion has exceeded the timing limits, DQ5 produces a
“1.”
Under both these conditions, the system must issue
the reset command to return the device to reading
array data.
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not
an erase operation has begun. (The sector erase
timer does not apply to the chip erase command.) If
additional sectors are selected for erasure, the entire
time-out also applies after each additional sector
erase command. When the time-out is complete, DQ3
switches from “0” to “1.” The system may ignore DQ3
if the system can guarantee that the time between
additional sector erase commands will always be less
than 50 µs. See also the “Sector Erase Command
Sequence” section.
After the sector erase command sequence is written,
the system should read the status on DQ7 (Data#
Polling) or DQ6 (Toggle Bit I) to ensure the device has
accepted the command sequence, and then read
DQ3. If DQ3 is “1”, the internally controlled erase
cycle has begun; all further commands (other than
Erase Suspend) are ignored until the erase operation
is complete. If DQ3 is “0”, the device will accept addi-
tional sector erase commands. To ensure the
command has been accepted, the system software
should check the status of DQ3 prior to and following
each subsequent sector erase command. If DQ3 is
high on the second status check, the last command
might not have been accepted. Table 2 shows the
outputs for DQ3.