CS2100CP-CZZR Cirrus Logic Inc, CS2100CP-CZZR Datasheet
CS2100CP-CZZR
Specifications of CS2100CP-CZZR
CS2100CP-CZZR
Related parts for CS2100CP-CZZR
CS2100CP-CZZR Summary of contents
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Fractional-N Clock Multiplier Features Clock Multiplier / Jitter Reduction – Generates a Low Jitter MHz Clock from a Jittery or Intermittent MHz Clock Source Highly Accurate PLL Multiplication Factor – Maximum ...
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TABLE OF CONTENTS 1. PIN DESCRIPTION ................................................................................................................................. 4 2. TYPICAL CONNECTION DIAGRAM ..................................................................................................... 5 3. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 6 RECOMMENDED OPERATING CONDITIONS .................................................................................... 6 ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 6 DC ELECTRICAL CHARACTERISTICS ................................................................................................ 6 AC ELECTRICAL CHARACTERISTICS ................................................................................................ 7 ...
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Enable Device Configuration Registers 1 (EnDevCfg1) ........................................................ 27 8.4 Global Configuration (Address 05h) ............................................................................................... 27 8.4.1 Device Configuration Freeze (Freeze) ................................................................................ 27 8.4.2 Enable Device Configuration Registers 2 (EnDevCfg2) ....................................................... 27 8.5 Ratio (Address 06h - 09h) .............................................................................................................. 28 ...
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PIN DESCRIPTION VD GND CLK_OUT AUX_OUT CLK_IN Pin Name # Pin Description VD 1 Digital Power (Input) - Positive power supply for the digital and analog sections. GND 2 Ground (Input) - Ground reference. CLK_OUT 3 PLL Clock Output ...
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TYPICAL CONNECTION DIAGRAM 1 Note Notes: 1. Resistors 2 required for I C Ω operation. System MicroController Frequency Reference Low-Jitter Timing Reference Crystal DS840PP2 Confidential Draft 3/18/09 0.1 µF Ω ...
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CHARACTERISTICS AND SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS GND = 0 V; all voltages with respect to ground. Parameters DC Power Supply Ambient Operating Temperature (Power Applied) Notes: 1. Device functionality is not guaranteed or implied outside of these limits. Operation ...
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AC ELECTRICAL CHARACTERISTICS Test Conditions (unless otherwise specified 3 3 pF. L Parameters Crystal Frequency Reference Clock Input Frequency Reference Clock Input Duty Cycle Internal System Clock Frequency Clock Input Frequency ...
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CONTROL PORT SWITCHING CHARACTERISTICS- I²C FORMAT Inputs: Logic 0 = GND; Logic 1 = VD; C Parameter SCL Clock Frequency Bus Free-Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low Time Clock High Time Setup ...
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CONTROL PORT SWITCHING CHARACTERISTICS - SPI FORMAT Inputs: Logic 0 = GND; Logic 1 = VD; C Parameter CCLK Clock Frequency CCLK Edge to CS Falling CS High Time Between Transmissions CS Falling to CCLK Edge CCLK Low Time CCLK ...
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ARCHITECTURE OVERVIEW 4.1 Delta-Sigma Fractional-N Frequency Synthesizer The core of the CS2100 is a Delta-Sigma Fractional-N Frequency Synthesizer which has very high-resolu- tion for Input/Output clock ratios, low phase noise, very wide range of output frequencies and the ability ...
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Delta-Sigma Fractional-N Frequency Synthesizer Timing Reference Clock Digital PLL and Fractional-N Logic Frequency Reference Clock DS840PP2 Confidential Draft 3/18/09 Phase Internal Voltage Controlled Comparator Loop Filter Oscillator Fractional-N Divider Delta-Sigma Modulator N Digital Filter Frequency Comparator for Frac-N Generation Output ...
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APPLICATIONS 5.1 Timing Reference Clock Input The low jitter timing reference clock (RefClk) can be provided by either an external reference clock or an external crystal in conjunction with the internal oscillator. In order to maintain a stable and ...
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External Reference Clock (REF_CLK) For operation with an externally generated REF_CLK signal, XTI/REF_CLK should be connected to the reference clock source and XTO should be left unconnected or pulled low through a 47 kΩ resistor to GND. 5.2 Frequency ...
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Electrical Characteristics” on page 7 output will resume. CLK_IN ClkSkipEn PLL_OUT ClkOutUnl=0 UNLOCK If CLK_IN is removed and then reapplied within 2 have no effect and the PLL output will continue until CLK_IN ...
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Adjusting the Minimum Loop Bandwidth for CLK_IN The CS2000 allows the minimum loop bandwidth of the Digital PLL to be adjusted between 1 Hz and 128 Hz using the ClkIn_BW[2:0] bits. The minimum loop bandwidth of the Digital PLL ...
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Output to Input Frequency Ratio Configuration 5.3.1 User Defined Ratio (R The User Defined Ratio, R which determines the basis for the desired input to output clock ratio. The 32-bit R in either a high resolution (12.20) or high ...
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Manual Ratio Modifier (R-Mod) The manual Ratio Modifier is used to internally multiply/divide the R space remains unchanged). The available options for R The R-Mod value selected by RModSel[2:0] is always used in the calculation for the Effective Ratio ...
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Frequency Range Indicator would then reflect the frequency range of the audio sample rate 512 would then generate the audio oversampling clocks as shown in UD Inferred Audio Sample Rate FsDetect[1:0] when SysClk=12.288 ...
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Ratio Configuration Summary The R is the user defined ratio stored in the register space. The resolution for the R UD setting LFRatioCfg. R-Mod is applied if selected. The user defined ratio, ratio modifier, and automatic ratio modifier make ...
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PLL Clock Output The PLL clock output pin (CLK_OUT) provides a buffered version of the output of the frequency synthesizer. The driver can be set to high-impedance with the ClkOutDis bit. The output from the PLL automatically drives a ...
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Clock Output Stability Considerations 5.6.1 Output Switching CS2100 is designed such that re-configuration of the clock routing functions do not result in a partial clock period on any of the active outputs (CLK_OUT and/or AUX_OUT). In particular, enabling or ...
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SPI / I²C CONTROL PORT The control port is used to access the registers and allows the device to be configured for the desired operational modes and formats. The operation of the control port may be completely asynchronous with ...
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R/W bit. If the operation is a write, the next byte is the Memory Address Point- er (MAP) which selects the register to be read or written. If the operation is a read, ...
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Memory Address Pointer The Memory Address Pointer (MAP) byte comes after the address byte and selects the register to be read or written. Refer to the pseudocode above for implementation details. 6.3.1 Map Auto Increment The device has MAP ...
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REGISTER DESCRIPTIONS In I²C Mode all registers are read/write unless otherwise stated. In SPI mode all registers are write only. All “Re- served” registers must maintain their default state to ensure proper functional operation. The default state of each ...
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Auto R-Modifier Enable (AutoRMod) Controls the automatic ratio modifier function. AutoRMod Automatic R-Mod State 0 Disabled. 1 Enabled. Application: “Automatic Ratio Modifier (Auto R-Mod)” on page 17 8.2.4 Auxiliary Output Disable (AuxOutDis) This bit controls the output driver for ...
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Auxiliary Output Source Selection (AuxOutSrc[1:0]) Selects the source of the AUX_OUT signal. AuxOutSrc[1:0] Auxiliary Output Source 00 RefClk. 01 CLK_IN. 10 CLK_OUT. 11 PLL Lock Status Indicator. Application: “Auxiliary Output” on page 20 Note: When set to 11, AuxLckCfg ...
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Ratio (Address 06h - 09h MSB ............................................................................................................................ MSB-8 ............................................................................................................................ LSB+15 ............................................................................................................................ LSB+7 ............................................................................................................................ These registers contain the User Defined Ratio as shown in the page 24. These 4 registers form a single 32-bit ratio value ...
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Function Configuration 2 (Address 17h Reserved Reserved Reserved 8.7.1 Enable PLL Clock Output on Unlock (ClkOutUnl) Defines the state of the PLL output during the PLL unlock condition. ClkOutUnl Clock Output Enable Status 0 Clock outputs are ...
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CALCULATING THE USER DEFINED RATIO Note: The software for use with the evaluation kit has built in tools to aid in calculating and converting the User Defined Ratio. This section is for those who are not interested in the ...
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DIMENSIONS 10L MSOP (3 mm BODY) PACKAGE DRAWING TOP VIEW INCHES DIM MIN 0.0295 b 0.0059 c 0.0031 D -- 0.1181 BSC E -- 0.1929 BSC E1 -- 0.1181 ...
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... Temp Range Container Pb-Free Grade 10L-MSOP Yes Commercial 10L-MSOP Yes - Yes - Changes 6. 7. Figure 18 on page 23. “Ordering Information” on page 32. CS2100-CP Order# -10° to +70°C Rail CS2100CP-CZZ Tape and -10° to +70°C CS2100CP-CZZR Reel - - CDK2000-CLK “AC Electrical Char- 21. page 27 and page 27. DS840PP2 ...