CS2300P-CZZ Cirrus Logic Inc, CS2300P-CZZ Datasheet - Page 24

• Manufacturer Part Number: CS2300P-CZZ
• Description: IC General Purpose PLL LCO
• Manufacturer: Cirrus Logic Inc
• Type: Fanout Distribution, Fractional N Synthesizerr

Specifications of CS2300P-CZZ

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 1:2
• Differential - Input:output: No/No
• Frequency - Max: 75MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.1 V ~ 3.5 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Frequency-max: 75MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1494 - BOARD EVAL GEN PURPOSE PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1755; CS2300P-CZZ

24
7. CALCULATING THE USER DEFINED RATIO
Note:
Most calculators do not interpret the fixed point binary representation which the CS2300-OTP uses to define the
output to input clock ratio (see
to generate a binary or hex value for Ratio
ming Information” on page 25
7.1
7.2
The software for use with the evaluation kit has built in tools to aid in calculating and converting the User
Defined Ratio. This section is for those who would like to know more about how the User Defined Ratio is
calculated and stored.
High Resolution 12.20 Format
To calculate the User Defined Ratio (R
cy by the given input clock (CLK_IN). Then multiply the desired ratio by the scaling factor of 2
scaled decimal representation; then use the decimal to binary/hex conversion function on a calculator and
write to the register. A few examples have been provided in
High Multiplication 20.12 Format
To calculate the User Defined Ratio (R
cy by the given input clock (CLK_IN). Then multiply the desired ratio by the scaling factor of 2
scaled decimal representation; then use the decimal to binary/hex conversion function on a calculator and
write to the register. A few examples have been provided in
Desired Output to Input Clock Ratio
Desired Output to Input Clock Ratio
11.2896 MHz/59.97 Hz =188254.127...
(output clock/input clock)
(output clock/input clock)
12.288 MHz/10 MHz=1.2288
12.288 MHz/60 Hz=204,800
11.2896 MHz/44.1 kHz=256
Section 5.4.1 on page
for more details on programming.
Table 5. Example 12.20 R-Values
Table 6. Example 20.12 R-Values
0-3
to be stored in one time programmable memory. Please see
Confidential Draft
UD
UD
) to store in the register(s), divide the desired output clock frequen-
) to store in the register(s), divide the desired output clock frequen-
(output clock/input clock)
(output clock/input clock)
13); However, with a simple conversion we can use these tools
3/18/09
Representation =
Representation =
Scaled Decimal
Scaled Decimal
268435456
838860800
771088904
1288490
Table
Table
5.
6.
•
•
2
2
20
12
Hex Representation of
Hex Representation of
00 13 A9 2A
2D F5 E2 08
Binary R
10 00 00 00
Binary R
32 00 00 00
CS2300-OTP
20
12
UD
UD
DS844PP2
“Program-
to get the
to get the