CS4350-DZZ Cirrus Logic Inc, CS4350-DZZ Datasheet - Page 26

• Manufacturer Part Number: CS4350-DZZ
• Description: IC 105dB 192kHz DAC W/PLL
• Manufacturer: Cirrus Logic Inc

Specifications of CS4350-DZZ

• Number Of Bits: 24
• Data Interface: Serial
• Number Of Converters: 2
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 290mW
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1517 - BOARD EVAL FOR CS4350 DAC
• Settling Time: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1184-5

26
6.3
6.3.1
SDA
SCL
START
SPI Mode
In SPI Mode, data is clocked into the serial control data line, CDIN, by the serial control port clock, CCLK
(see
signal and is used to control SPI writes to the control port. When the device detects a high-to-low transition
on the AD0/CS pin after power-up, SPI Mode will be selected. All signals are inputs and data is clocked in
on the rising edge of CCLK.
3. Once the device has transmitted the contents of the register pointed to by the MAP, issue an ACK.
4. If the INCR bit is set to 1, the device will continue to transmit the contents of successive registers.
5. If the INCR bit is set to 0 and further I²C reads from other registers are desired, it is necessary to
SPI Write
To write to the device, follow the procedure below while adhering to the control port switching specifica-
tions in
1. Bring CS low.
2. The address byte on the CDIN pin must then be 10011110 (R/W = 0).
3. Write to the memory address pointer, MAP. This byte points to the register to be written.
4. Write the desired data to the register pointed to by the MAP.
5. If the INCR bit (see
6. If the INCR bit is set to 0 and further SPI writes to other registers are desired, it is necessary to bring
1 0 0 1 0 AD1 AD0 R/W
0
Figure 20
MAP or the default address (see
device.
Continue providing a clock and issue an ACK after each byte until all the desired registers are read;
then initiate a STOP condition to the bus.
initiate a repeated START condition and follow the procedure detailed from steps 1 and 2 from the I²C
Write instructions, followed by step 1 of the I²C Read section. If no further reads from other registers
are desired, initiate a STOP condition to the bus.
written, then bring CS high.
CS high, and follow the procedure detailed from step 1. If no further writes to other registers are
desired, bring CS high
1
CHIP ADDRESS
”Switching Characteristics - Control Port - SPI Format” on page
2
3
for the clock to data relationship). There are no AD0 or AD1 pins. Pin CS is the chip select
4
5
6
7
Section
ACK
8
Figure 19. Control Port Timing, I²C Mode
INC
9
10 11
6.1) is set to 1, repeat the previous step until all the desired registers are
6
MAP BYTE
5
12
Section
4
13 14 15
3
2
6.4.2) if an I²C read is the first operation performed on the
1
16 17 18
0
ACK
7
19
6
DATA
24 25
1
0
ACK
26
27 28
7
15.
DATA +1
6
1
0
7
DATA +n
6
1
CS4350
0
DS691F1
ACK
STOP