CS5368-DQZR Cirrus Logic Inc, CS5368-DQZR Datasheet - Page 31

• Manufacturer Part Number: CS5368-DQZR
• Description: IC,A/D CONVERTER,OCTAL,24-BIT,QFP,48PIN
• Manufacturer: Cirrus Logic Inc

36
5.4
R/W
R
02h (OVFL) Overflow Status Register
Bit[6] CLKMODE Setting this bit puts the part in 384X mode (divides XTI by 1.5), and clearing
the bit invokes 256X mode (divide XTI by 1.0 - pass through).
Bits[5:4] MDIV[1:0] Each bit selects an XTI divider. When either bit is low, an XTI divide by 1
function is selected. When either bit is HIGH, an XTI divide by 2 function is selected. With both
bits HIGH, XTI is divided by 4.
The table below shows the composite XTI division using both CLKMODE and MDIV[1:0].
Bits[3:2] DIF[1:0] Determine which data format the serial audio interface is using to clock out da-
ta.
Bits[1:0] MODE[1:0] This bit field determines the device sample rate range and whether it is op-
erating as an audio clocking Master or Slave.
Default:
Note: This register interacts with Register 03h, the Overflow Mask Register.
The Overflow Status Register is used to indicate an individual overflow in a channel. If an overflow
condition on any channel is detected, the corresponding bit in this register is asserted (low) in ad-
dition to the open drain active low OVFL pin going low. Each overflow status bit is sticky and is
cleared only when read, providing full interrupt capability.
CLKMODE,MDIV[1],MDIV[0]
OVFL8
7
DIF[1:0]
0x00 Left Justified format
0x01 I²S format
0x02 TDM format
0x03 TDM format
MODE[1:0]
0x00 Single-Speed Mode Master
0x01 Double-Speed Mode Master
0x02 Quad-Speed Mode Master
0x03 Slave Mode all speeds
0xFF, no overflows have occurred.
001 or 010
101 or 110
000
100
011
111
OVFL7
6
OVFL6
5
OVFL5
4
DESCRIPTION
Divide-by-1.5
Divide-by-1
Divide-by-2
Divide-by-3
Divide-by-4
Unused
OVFL4
3
OVFL3
2
OVFL2
1
CS5368
OVFL1
DS624A1
0