CS5376A-IQZR Cirrus Logic Inc, CS5376A-IQZR Datasheet - Page 41

• Manufacturer Part Number: CS5376A-IQZR
• Description: IC LP Multi-Channel Decimation Filter
• Manufacturer: Cirrus Logic Inc

Specifications of CS5376A-IQZR

• Filter Type: Digital
• Number Of Filters: 4
• Max-order: 2nd
• Voltage - Supply: 3 V ~ 5 V
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1778 - EVALUATION BOARD FOR CS5376
• Frequency - Cutoff Or Center: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.DIGITAL FILTER INITIALIZATION
The CS5376A digital filter consists of three multi-
stage sections: a three stage SINC filter, a two stage
FIR filter, and a two stage IIR filter.
To initialize the digital filter, FIR and IIR coeffi-
cient sets are selected using configuration com-
mands and the FILTCFG register (0x20) is written
to select the output filter stage, the output word
rate, and the number of enabled channels. The dig-
ital filter clock rate is selected by writing the CON-
FIG register (0x00).
11.1 Filter Coefficient Selection
Selection of SINC filter coefficients is not required
as they are selected automatically based on the pro-
grammed output word rate.
Digital filter FIR and IIR coefficients are selected
using the ‘Write FIR Coefficients’ and ‘Write IIR
Coefficients’, or the ‘Write ROM Coefficients’
configuration commands. When writing the FIR
and IIR coefficients from ROM, a data word selects
an on-chip coefficient set for each filter stage. Fig-
ure 22 shows the format of the coefficient selection
DS612F4
Modulator
512 kHz
Input
Correction
DC Offset
& Gain
SINC Filter
2 - 64000
FIR1
4
Figure 21. Digital Filter Stages
Output to High Speed Serial Data Port (SD Port)
FIR2
2
Output Rate 4000 SPS ~ 1 SPS
word, and the available coefficient sets for each se-
lection.
Characteristics of the on-chip digital filter coeffi-
cients are discussed in the ‘SINC Filter’, ‘FIR Fil-
ter’, and ‘IIR Filter’ sections of this data sheet.
11.2 Filter Configuration Options
Digital filter parameters are selected by bits in the
FILTCFG register (0x20), and the digital filter
clock rate is selected by bits in the CONFIG regis-
ter (0x00).
11.2.1 Output Filter Stage
The digital filter can output data following any
stage in the filter chain. The output filter stage is se-
lected by the FSEL bits in the FILTCFG register.
Taking data from the SINC or FIR1 filter stages re-
duces the overall decimation of the filter chain and
increases the output rate, as discussed in the fol-
lowing section. Taking data from FIR2, IIR1, IIR2,
or IIR3 results in data at the selected rate.
1st Order
IIR1
2nd Order
IIR2
CS5376A
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