CS5381-KSZR Cirrus Logic Inc, CS5381-KSZR Datasheet - Page 4

• Manufacturer Part Number: CS5381-KSZR
• Description: IC,A/D CONVERTER,DUAL,24-BIT,SOP,24PIN
• Manufacturer: Cirrus Logic Inc

Specifications of CS5381-KSZR

• Number Of Bits: 24
• Sampling Rate (per Second): 216k
• Data Interface: Serial
• Number Of Converters: 2
• Power Dissipation (max): 445mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (0.300", 7.50mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1592 - REFERENCE DESIGN CS5381 AUD ADC598-1008 - BOARD EVAL FOR CS5381 192KHZ ADC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4
1. PIN DESCRIPTIONS
RST
M/S
LRCK
SCLK
MCLK
VD
GND
VL
SDOUT
MDIV
HPF
I²S/LJ
M0
M1
OVFL
AINL+
AINL-
VA
AINR-
AINR+
VQ
REF_GND
FILT+
Pin Name
16, 17
20, 21
13,14
7,18
10
12
15
19
22
23
24
11
#
1
2
3
4
5
6
8
9
Pin Description
Reset (Input) - The device enters a low power mode when low.
Master/Slave Mode (Input) - Selects operation as either clock master or slave.
Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the
serial audio data line.
Serial Clock (Input/Output) - Serial clock for the serial audio interface.
Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters.
Digital Power (Input) - Positive power supply for the digital section.
Ground (Input) - Ground reference. Must be connected to analog ground.
Logic Power (Input) - Positive power for the digital input/output.
Serial Audio Data Output (Output) - Output for two’s complement serial audio data.
MCLK Divider (Input) - Enables a master clock divide by two function.
High-Pass Filter Enable (Input) - Enables the Digital High-Pass Filter.
Serial Audio Interface Format Select (Input) -Selects either the left-justified or I²S format for the SAI.
Mode Selection (Input) - Determines the operational mode of the device.
Overflow (Output, open drain) - Detects an overflow condition on both left and right channels.
Differential Left Channel Analog Input (Input) - Signals are presented differentially to the delta-sigma
modulators via the AINL+/- pins.
Analog Power (Input) - Positive power supply for the analog section.
Differential Right Channel Analog Input (Input) -Signals are presented differentially to the delta-
sigma modulators via the AINR+/- pins.
Quiescent Voltage (Output) - Filter connection for the internal quiescent reference voltage.
Reference Ground (Input) - Ground reference for the internal sampling circuits.
Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.
SDOUT
MCLK
LRCK
SCLK
I²S/LJ
MDIV
GND
RST
HPF
M/S
VD
VL
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
FILT+
REFGND
VQ
AINR+
AINR-
VA
GND
AINL-
AINL+
OVFL
M1
M0
CS5381
DS563F2