CY14B101LA-SP45XIT Cypress Semiconductor Corp, CY14B101LA-SP45XIT Datasheet - Page 25

• Manufacturer Part Number: CY14B101LA-SP45XIT
• Description: CY14B101LA-SP45XIT
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY14B101LA-SP45XIT

• Format - Memory: RAM
• Memory Type: NVSRAM (Non-Volatile SRAM)
• Memory Size: 1M (128K x 8)
• Speed: 45ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document #: 001-42879 Rev. *K
Document Title: CY14B101LA, CY14B101NA 1-Mbit (128 K × 8/64 K × 16) nvSRAM
Document Number: 001-42879
Rev.
*C
*D
*G
*H
*E
*F
*K
*J
*I
ECN No.
2733909
2757348
2793420
2839453
2894534
2922854
2958648
3074645
3134300
GVCH/PYRS
GVCH/AESA
Change
Orig. of
GVCH
GVCH
GVCH
GVCH
GVCH
GVCH
GVCH
Submission
01/11/2011
07/09/09
08/28/09
10/27/09
01/06/10
03/17/10
04/26/10
06/22/10
10/29/10
Date
Moved datasheet status from Preliminary to Final
Updated 48-pin SSOP package diagram
Removed 48-ball FBGA package and added 54-pin TSOP II Package
Corrected typo error in pin diagram of 48-pin SSOP
Page 4; Added note to AutoStore Operation description
Page 4; Updated Hardware STORE (HSB) Operation description
Page 5; Updated Software STORE Operation description
Added best practices
Updated V
Updated t
Updated footnote 24 and added footnote 29
Removed commercial temperature related specs
Updated thermal resistance values for all the packages
Changed STORE cycles to QuantumTrap from 200 K to 1 Million
Added
Removed inactive parts from
Updated links in
Updated
Table
Hardware STORE
Table
Updated HSB pin operation in
Updated footnote 36
Updated package diagram 51-85087
Added 48-Ball FBGA package related information
Updated package diagram 51-85128
Updated template and added Acronym table
48 FBGA package: 16 Mb address expansion is not supported
Removed inactive parts from
CY14B101NA-ZS20XIT, CY14B101NA-ZS20XI
Added
Updated style format
Updated input capacitance for BHE and BLE pin
Updated input and output capacitance for HSB pin
Fixed typo in
1: Added more clarity on HSB pin operation
3: Added more clarity on BHE/BLE pin operation
Contents
Document Conventions
Package
DELAY
HDIS
Figure 11
parameter description
parameter description
Sales, Solutions, and Legal
Diagrams.
Operation: Added more clarity on HSB pin operation
Description of Change
Ordering Information
Ordering Information
Figure 11
table
Information.
table.
table.
CY14B101NA
CY14B101LA
Page 25 of 26
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