CY62147EV30LL-45BVI Cypress Semiconductor Corp, CY62147EV30LL-45BVI Datasheet

CY62147EV30LL-45BVI

CY62147EV30LL-45BVI

Manufacturer Part Number
CY62147EV30LL-45BVI
Description
CY62147EV30LL-45BVI
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY62147EV30LL-45BVI

Format - Memory
RAM
Memory Type
SRAM
Memory Size
4M (256K x 16)
Speed
45ns
Interface
Parallel
Voltage - Supply
2.2 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
48-VFBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY62147EV30LL-45BVI
Manufacturer:
BGA
Quantity:
465
Part Number:
CY62147EV30LL-45BVI
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Part Number:
CY62147EV30LL-45BVIT
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Features
Functional Description
The CY62147EV30 is a high performance CMOS static RAM
(SRAM) organized as 256K words by 16 bits. This device
features advanced circuit design to provide ultra low active
current. It is ideal for providing More Battery Life™ (MoBL
portable applications such as cellular telephones. The device
Cypress Semiconductor Corporation
Document Number: 38-05440 Rev. *J
Note
Logic Block Diagram
1. BGA packaged device is offered in single CE and dual CE options. In this data sheet, for a dual CE device, CE refers to the internal logical combination of CE
Very high speed: 45 ns
Temperature ranges
Wide voltage range: 2.20 V to 3.60 V
Pin compatible with CY62147DV30
Ultra low standby power
Ultra low active power
Easy memory expansion with CE
Automatic power-down when deselected
Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
Available in Pb-free 48-ball very fine ball grid array (VFBGA)
(single/dual CE option) and 44-pin thin small outline package
(TSOP) II packages
Byte power-down feature
Industrial: –40 °C to +85 °C
Typical standby current: 1 A
Maximum standby current: 7 A (Industrial)
Typical active current: 2 mA at f = 1 MHz
CE
2
such that when CE
1
is LOW and CE
POWER DOWN
CIRCUIT
[1]
2
is HIGH, CE is LOW. For all other cases CE is HIGH.
and OE features
A
A
A
A
A
A
A
A
A
A
A
6
5
4
3
2
1
0
10
9
8
7
198 Champion Court
CE
BHE
BLE
) in
COLUMN DECODER
DATA IN DRIVERS
RAM Array
256K x 16
also has an automatic power down feature that significantly
reduces power consumption when addresses are not toggling.
Placing the device into standby mode reduces power
consumption by more than 99 percent when deselected (CE
HIGH or both BLE and BHE are HIGH). The input and output pins
(I/O
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O
specified on the address pins (A
Enable (BHE) is LOW, then data from I/O pins (I/O
I/O
(A
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appear on I/O
Byte High Enable (BHE) is LOW, then data from memory
appears on I/O
complete description of read and write modes.
For best practice recommendations, refer to the Cypress
application note
4-Mbit (256K x 16) Static RAM
Deselected (CE HIGH)
Outputs are disabled (OE HIGH)
Both Byte High Enable and Byte Low Enable are disabled
(BHE, BLE HIGH)
Write operation is active (CE LOW and WE LOW)
0
15
0
through A
) is written into the location specified on the address pins
through I/O
San Jose
17
8
).
AN1064, SRAM System
15
to I/O
) are placed in a high impedance state when:
0
through I/O
,
15
CA 95134-1709
. See the
CY62147EV30 MoBL
I/O
I/O
0
8
–I/O
–I/O
BHE
WE
CE
OE
BLE
7
7
15
) is written into the location
[1]
0
Truth Table on page 10
through A
Revised January 31, 2011
Guidelines.
17
). If Byte High
408-943-2600
0
8
to I/O
through
1
for a
and
7
®
. If
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CY62147EV30LL-45BVI Summary of contents

Page 1

... LOW and CE is HIGH LOW. For all other cases CE is HIGH Cypress Semiconductor Corporation Document Number: 38-05440 Rev. *J 4-Mbit (256K x 16) Static RAM also has an automatic power down feature that significantly reduces power consumption when addresses are not toggling. Placing the device into standby mode reduces power consumption by more than 99 percent when deselected (CE HIGH or both BLE and BHE are HIGH) ...

Page 2

Contents Product Portfolio .............................................................. 3 Pin Configuration ............................................................. 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Capacitance ...................................................................... 4 Thermal Resistance........................................................... 5 Data Retention Characteristics ....................................... 5 Switching Characteristics ................................................ 6 Switching Waveforms ...................................................... 7 ...

Page 3

... Product Portfolio Product Range Min CY62147EV30LL Industrial 2.2 Pin Configuration Figure 1. 48-Ball VFBGA (Single Chip Enable BLE I/O BHE I/O I I/O I I/O I Notes 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured ...

Page 4

... Document Number: 38-05440 Rev input voltage Output current into outputs (LOW) ............................. 20 mA Static discharge voltage .......................................... >2001 V (MIL-STD-883, method 3015) Latch-up current ...................................................... >200 mA Operating Range Device + 0.3 V) CCmax CY62147EV30LL Industrial –40 °C to +85 ° 0.3 V) CCmax Test Conditions Min 2.0 > 2.70 V 2.4 CC – ...

Page 5

Thermal Resistance [11] Parameter Description  Thermal resistance JA (junction to ambient)  Thermal resistance JC (junction to case OUTPUT INCLUDING JIG AND SCOPE Equivalent to: THEVENIN EQUIVALENT Parameters ...

Page 6

Switching Characteristics Over the Operating Range [17, 18] Parameter Read Cycle t Read cycle time RC t Address to data valid AA t Data hold from address change OHA t CE LOW to data valid ACE t OE LOW to ...

Page 7

Switching Waveforms Figure 6. Read Cycle No. 1: Address Transition Controlled ADDRESS PREVIOUS DATA VALID DATA OUT Figure 7. Read Cycle No Controlled ADDRESS CE t ACE OE t LZOE BHE/BLE t DBE t LZBE HIGH IMPEDANCE DATA ...

Page 8

Switching Waveforms (continued) Figure 8. Write Cycle No Controlled ADDRESS BHE/BLE OE NOTE 30 DATA I/O t HZOE Figure 9. Write Cycle No Controlled ADDRESS CE WE BHE/BLE OE DATA I/O NOTE ...

Page 9

Switching Waveforms (continued) Figure 10. Write Cycle No Controlled, OE LOW ADDRESS CE BHE/BLE DATA I/O NOTE 33 t HZWE Figure 11. Write Cycle No. 4: BHE/BLE Controlled, OE LOW ADDRESS CE BHE/BLE t SA ...

Page 10

Truth Table CE [34, 35 BHE BLE ...

Page 11

... Ordering Information Speed Ordering Code (ns) 45 CY62147EV30LL-45BVI CY62147EV30LL-45BVXI CY62147EV30LL-45B2XI CY62147EV30LL-45ZSXI Contact your local Cypress sales representative for availability of these parts. Ordering Code Definitions 621 4 E V30 LL 45 xxx CY 7 Notes 36. This BGA package is offered with single chip enable. 37. This BGA package is offered with dual chip enable. ...

Page 12

Package Diagrams Figure 12. 48-Ball VFBGA ( mm), 51-85150 Document Number: 38-05440 Rev. *J ® CY62147EV30 MoBL 51-85150 *F 51-85150 *F Page [+] Feedback ...

Page 13

Package Diagrams (continued) Acronyms Acronym Description CMOS complementary metal oxide semiconductor I/O input/output SRAM static random access memory VFBGA very fine ball grid array TSOP thin small outline package Document Number: 38-05440 Rev. *J Figure 13. 44-Pin TSOP II, 51-85087 ...

Page 14

... Added Preliminary Automotive-A information Added footnote #9 related to I Added footnote #14 related AC timing parameters Converted Automotive-A and Automotive -E specs from preliminary to final Added -45B2XI part (Dual CE option) Added CY62147EV30LL-45ZSXA in the ordering information table Updated package diagrams. Added Contents. Updated links in Sales, Solutions, and Legal Added Note 23 ...

Page 15

Document Title: CY62147EV30 MoBL Document Number: 38-05440 Orig. of Submission Rev. ECN No. Change *J 3123973 RAME 01/31/2011 Document Number: 38-05440 Rev. *J ® 4-Mbit (256K x 16) Static RAM Description of Change Date Separated Industrial and Auto parts from ...

Page 16

... Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement ...

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