CY62147EV30LL-45BVXIT Cypress Semiconductor Corp, CY62147EV30LL-45BVXIT Datasheet - Page 6

CY62147EV30LL-45BVXIT

CY62147EV30LL-45BVXIT

Manufacturer Part Number
CY62147EV30LL-45BVXIT
Description
CY62147EV30LL-45BVXIT
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY62147EV30LL-45BVXIT

Format - Memory
RAM
Memory Type
SRAM
Memory Size
4M (256K x 16)
Speed
45ns
Interface
Parallel
Voltage - Supply
2.2 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
48-VFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Part Number
Manufacturer
Quantity
Price
Part Number:
CY62147EV30LL-45BVXIT
Manufacturer:
TriQuint
Quantity:
12
Part Number:
CY62147EV30LL-45BVXIT
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Switching Characteristics
Over the Operating Range
Notes
Document Number: 38-05440 Rev. *J
Read Cycle
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Write Cycle
t
t
t
t
t
t
t
t
t
t
t
17. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns (1V/ns) or less, timing reference levels of V
18. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See application note
19. At any temperature and voltage condition, t
20. t
21. The internal write time of the memory is defined by the overlap of WE, CE = V
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
DBE
LZBE
HZBE
WC
SCE
AW
HA
SA
PWE
BW
SD
HD
HZWE
LZWE
levels of 0 to V
signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
HZOE
, t
Parameter
HZCE
, t
[21]
HZBE
CC(typ)
, and t
, and output loading of the specified I
HZWE
transitions are measured when the outputs enter a high impedance state.
[17, 18]
Read cycle time
Address to data valid
Data hold from address change
CE LOW to data valid
OE LOW to data valid
OE LOW to LOW Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to power-up
CE HIGH to power-down
BLE/BHE LOW to data valid
BLE/BHE LOW to Low Z
BLE/BHE HIGH to HIGH Z
Write cycle time
CE LOW to write end
Address setup to write end
Address hold from write end
Address setup to write start
WE pulse width
BLE/BHE LOW to write end
Data setup to write end
Data hold from write end
WE LOW to High Z
WE HIGH to Low Z
HZCE
is less than t
[19]
Description
[19, 20]
[19, 20]
[19]
[19]
[19, 20]
OL
/I
LZCE
OH
[19]
as shown in the
, t
[19, 20]
HZBE
is less than t
IL
, BHE, BLE, or both = V
AC Test Load and Waveforms on page
LZBE
, t
HZOE
is less than t
IL
. All signals must be active to initiate a write and any of these
Min
10
10
10
35
35
35
35
25
10
45
45
5
0
0
0
0
45 ns (Industrial)
LZOE
, and t
CY62147EV30 MoBL
5.
HZWE
is less than t
Max
AN13842
45
45
22
18
18
45
45
18
18
for further clarification.
LZWE
CC(typ)
for any device.
Page 6 of 16
/2, input pulse
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
®
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