CY7C024AV-20AXI Cypress Semiconductor Corp, CY7C024AV-20AXI Datasheet
CY7C024AV-20AXI
Specifications of CY7C024AV-20AXI
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CY7C024AV-20AXI Summary of contents
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... Decode [4] 12/13/14 A –A 0L 11/12/13L R/W L SEM L [5] BUSY L INT Notes 1. CY7C024AV and CY7C024BV are functionally identical –IO for x16 devices; IO –IO for x18 devices –IO for x16 devices; IO –IO for x18 devices –A for 4K devices; A –A for 8K devices BUSY is an output in master mode and an input in slave mode. ...
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... Pin Configurations 100 10L 11L IO 12L 7 IO 13L 8 GND 14L IO 11 15L CY7C024AV/024BV (4K × 16 GND Notes the CY7C025AV. 12L the CY7C025AV. 12R Document #: 38-06052 Rev. *M CY7C024AV/024BV/025AV/026AV Figure 1. 100-Pin TQFP (Top View CY7C025AV (8K × 16 CY7C0241AV/0251AV/036AV INT 65 L BUSY 64 L GND 63 M/S 62 BUSY ...
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... NC 4 IO10L 5 IO11L 6 IO12L 7 IO13L 8 GND 9 IO14L 10 IO15L 11 VCC 12 GND 13 IO0R 14 IO1R 15 IO2R 16 VCC 17 IO3R 18 IO4R 19 IO5R 20 IO6R Notes the CY7C0251AV. 12L the CY7C0251AVC. 12R Document #: 38-06052 Rev. *M CY7C024AV/024BV/025AV/026AV Figure 2. 100-Pin TQFP (Top View CY7C0241AV (4K × 18) CY7C0251AV (8K × 18 CY7C026AV (16K × 16 ...
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... Typical Operating Current Typical Standby Current for I SB1 (Both ports TTL Level) Typical Standby Current for I SB3 (Both ports CMOS Level) Document #: 38-06052 Rev. *M CY7C024AV/024BV/025AV/026AV Figure 3. 100-Pin TQFP (Top View CY7C036AV (16K × 18 CY7C024AV/024BV/025AV/026AV CY7C024AV/024BV/025AV/026AV CY7C0241AV/0251AV/036AV -20 20 120 35 10 CY7C0241AV/0251AV/036AV 13L INT 65 L ...
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... CE pins. Data is available t asserted. If the user wants to access a semaphore flag, then the SEM pin and OE must be asserted. Interrupts The upper two memory locations are for message passing. The highest memory CY7C024AV/024BV/41AV/1FFF for the CY7C025AV/51AV, for 8K devices; A –A for 16K –IO for x18 devices) ...
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... CY7C026AV/36AV) is the mailbox for the right port and the second highest memory location (FFE for the CY7C024AV/024BV/41AV/1FFE for the CY7C025AV/51AV, 3FFE for the CY7C026AV/36AV) is the mailbox for the left port. When one port writes to the other port’s mailbox, an interrupt is generated to the owner ...
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... Left port writes 1 to semaphore Notes 10. See Functional Description on page 5 for specific highest memory locations by device. 11. If BUSY =L, then no change. R 12. If BUSY =L, then no change. L 13. See Functional Description on page 5 for specific addresses by device. Document #: 38-06052 Rev. *M CY7C024AV/024BV/025AV/026AV Outputs SEM IO – High Z High Z H High Z High Z ...
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... Tested initially and after any design or process changes that may affect these parameters. Document #: 38-06052 Rev. *M CY7C024AV/024BV/025AV/026AV DC Input Voltage Output Current into Outputs (LOW) ............................. 20 mA Static Discharge Voltage.......................................... > 2001V Latch-up Current.................................................... > 200 mA Operating Range Range Commercial [16] Industrial + 0.5V CC CY7C024AV/024BV/025AV/026AV CY7C0241AV/0251AV/036AV Min =3.3V) 2.4 2.0 [17] –0.3 –10 –10 Com’l. [16] Ind. Com’l. ...
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... This parameter is guaranteed but not tested. For information on port to port delay through RAM cells from writing port to reading port, refer to Document #: 38-06052 Rev. *M CY7C024AV/024BV/025AV/026AV Figure 4. AC Test Loads and Waveforms R = 250 TH OUTPUT C = 30pF V = 1.4V TH (b) Thévenin Equivalent (Load 1) ALL INPUT PULSES 90% 90% 10% 10% CY7C024AV/024BV/025AV/026AV Description Min less than t and t HZCE LZCE HZOE CY7C0241AV/0251AV/036AV 3. 590 OUTPUT 435 ...
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... For information on port to port delay through RAM cells from writing port to reading port, refer to 26. Test conditions used are Load 2. 27 calculated parameter and is the greater of t BDD 28 GND 25C. This parameter is guaranteed but not tested Document #: 38-06052 Rev. *M CY7C024AV/024BV/025AV/026AV CY7C024AV/024BV/025AV/026AV Description Min Timing and V ...
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... Figure 7. Read Cycle No. 3 (Either Port) ADDRESS DATA OUT Notes 29. R/W is HIGH for read cycles. 30. Device is continuously selected and 31 32. Address valid prior to or coincident with CE transition LOW. 33. To access RAM SEM = Document #: 38-06052 Rev. *M CY7C024AV/024BV/025AV/026AV t RC DATA VALID t ACE t DOE t LZOE t LZCE [29, 31, 32, 33 LZCE t ...
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... During this period, the IO pins are in the output state, and input signals must not be applied. 42. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high impedance state. Document #: 38-06052 Rev. *M CY7C024AV/024BV/025AV/026AV t WC ...
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... CE = HIGH for the duration of the above timing (both write and read cycle). 44 LOW (request semaphore 45. Semaphores are reset (available to both ports) at cycle start. 46 violated, the semaphore is definitely obtained by one side or the other, but which side gets the semaphore is unpredictable. SPS Document #: 38-06052 Rev. *M CY7C024AV/024BV/025AV/026AV t SAA VALID ADRESS SCE SOP t SD ...
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... Figure 12. Timing Diagram of Read with BUSY (M/S=HIGH) ADDRESS R R/W R DATA ADDRESS L BUSY L DATA OUTL Figure 13. Write Timing with Busy Input (M/S=LOW) R/W BUSY Note 47 LOW Document #: 38-06052 Rev. *M CY7C024AV/024BV/025AV/026AV CY7C0241AV/0251AV/036AV t WC MATCH t PWE t SD VALID MATCH t BLA t WDD t PWE [47 BHA ...
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... R Right Address Valid First: t ADDRESS ADDRESS MATCH ADDRESS L BUSY L Note 48 violated, the busy signal is asserted on one side or the other, but there is no guarantee to which side BUSY is asserted. PS Document #: 38-06052 Rev. *M CY7C024AV/024BV/025AV/026AV ADDRESS MATCH BLC ADDRESS MATCH BLC ADDRESS MISMATCH t t BLA ...
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... Left Side Clears INT : L ADDRESS R INT L Notes 49. t depends on which enable pin ( depends on which enable pin (CE INS INR L Document #: 38-06052 Rev. *M CY7C024AV/024BV/025AV/026AV Figure 16. Interrupt Timing Diagram t WC [49 [50] t INR t WC [49 [50] t INR ) is deasserted first R asserted last. L CY7C0241AV/0251AV/036AV t RC READ 7FFF ...
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... Ordering Information 4K x16 3.3V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code 15 CY7C024BV-15AXI 20 CY7C024AV-20AXC CY7C024AV-20AXI 25 CY7C024AV-25AXC CY7C024AV-25AXI 8K x16 3.3V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code 20 CY7C025AV-20AXC 25 CY7C025AV-25AXC CY7C025AV-25AXI 16K x16 3.3V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code 20 CY7C026AV-20AXC 25 CY7C026AV-25AC CY7C026AV-25AXC CY7C026AV-25AI CY7C026AV-25AXI Ordering Code Definitions ...
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... Package Diagram Figure 17. 100-Pin Pb-Free Thin Plastic Quad Flat Pack (TQFP) A100 Document #: 38-06052 Rev. *M CY7C024AV/024BV/025AV/026AV CY7C0241AV/0251AV/036AV 51-85048 *E Page [+] Feedback ...
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... IL Corrected CY7C024AC-25AXC to CY7C024AV-25AXC in Ordering Information Added to Part Ordering information: CY7C024AV-15AI, CY7C024AV-15AXI, CY7C024AV-20AI, CY7C024AV-20AXI, CY7C025AV-20AXI, CY7C026AV-20AXI 07/25/08 Updated note number 33 on page 12 from “R/W must be HIGH during all address transitions” to “R must be HIGH during all address transitions” 12/17/08 ...
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... Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-06052 Rev. *M All products and company names mentioned in this document may be the trademarks of their respective holders. CY7C024AV/024BV/025AV/026AV cypress.com/go/plc Revised March 30, 2011 CY7C0241AV/0251AV/036AV PSoC Solutions psoc ...