CY7C027V-25AXC Cypress Semiconductor Corp, CY7C027V-25AXC Datasheet
CY7C027V-25AXC
Specifications of CY7C027V-25AXC
CY7C027V-25AXC
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CY7C027V-25AXC Summary of contents
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... A –A 0L 14/15L R/W L SEM L [5] BUSY L INT Notes 1. CY7C027V, and CY7C027AV are functionally identical. 2. I/O –I/O for x16 devices; I/O –I/O for x18 devices I/O –I/O for x16 devices; I/O –I/O for x18 devices –A for 32K; A –A for 64K devices. ...
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... Semaphore Operation ................................................. 6 Maximum Ratings ............................................................. 7 Operating Range ............................................................... 7 Electrical Characteristics.................................................. 7 Capacitance ...................................................................... 7 Switching Characteristics ................................................ 8 Data Retention Mode ........................................................ 9 Document #: 38-06078 Rev. *D CY7C027V/027AV/028V CY7C037AV/038V Timing ................................................................................ 9 Switching Waveforms .................................................... 10 Ordering Information ...................................................... 17 32K x16 3.3 V Asynchronous Dual-Port SRAM ........ 17 64K x16 3.3 V Asynchronous Dual-Port SRAM ........ 17 32K x18 3.3 V Asynchronous Dual-Port SRAM ........ 17 64K x18 3 ...
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... LBL 10 UBL 11 CE0L 12 CE1L 13 SEML 14 VCC 15 R/WL 16 OEL 17 GND 18 GND 19 I/O15L 20 I/O14L 21 I/O13L 22 I/O12L 23 I/O11L 24 I/O10L Note 6. This pin is NC for CY7C027V/027AV. Document #: 38-06078 Rev. *D Figure 1. 100-Pin TQFP (Top View CY7C028V (64K x 16) CY7C027V/027AV (32K x 16 CY7C027V/027AV/028V CY7C037AV/038V A9R 74 A10R 73 A11R ...
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... SB3 Note 7. This pin is NC for CY7C037AV. Document #: 38-06078 Rev. *D Figure 2. 100-Pin TQFP (Top View CY7C038V (64K x 18) CY7C037AV (32K x 18 -15 15 125 35 10 A CY7C027V/027AV/028V CY7C037AV/038V A8R 74 A9R 73 A10R 72 A11R 71 A12R 70 A13R 69 A14R [7] 68 A15R 67 LBR 66 UBR 65 CE0R 64 CE1R 63 SEMR 62 ...
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... CY7C027V/037AV/027AV, FFFF for the CY7C028V/38V) is the mailbox for the right port and the second-highest memory location (7FFE for the CY7C027V/027AV/037AV, FFFE for the CY7C028V/38V) is the mailbox for the left port. When one port writes to the other port’s mailbox, an interrupt is generated to the owner ...
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... The operation of the interrupts and their interaction with Busy are summarized in Table 2. Busy The CY7C027V/027AV/028V and CY7037AV/038V provide on-chip arbitration to resolve simultaneous memory location access (contention). If both ports’ CEs are asserted and an address match occurs within t of each other, the busy logic determines which PS port has access ...
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... Input capacitance IN C Output capacitance OUT Notes 8. Pulse width < 20 ns. 9. Industrial parts are available in CY7C028V and CY7C038V, CY7C027V/027AV only. 10 1/t = All inputs cycling 1/t (except output enable means no address or control lines change. This applies only to inputs at CMOS level standby I MAX ...
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... HZCE LZCE HZOE CY7C027V/027AV/028V CY7C037AV/038V 3 590 OUTPUT 435 (c) Three-State Delay (Load 2) (Used for & HZWE LZWE including scope and jig) Unit -20 -25 Min Max Min ...
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... SEM address access time SAA Data Retention Mode The CY7C027V/027AV/028V and CY7037AV/038V are de- signed with battery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules ensure data retention: 1. Chip Enable (CE) must be held HIGH during data retention, within ...
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... Document #: 38-06078 Rev DATA VALID t ACE t DOE t LZOE t LZCE [23, 25, 26, 27 LZCE t ABE t ACE t LZCE . This waveform cannot be used for semaphore reads access semaphore SEM = CY7C027V/027AV/028V CY7C037AV/038V [23, 24, 25] t OHA [23, 26, 27] t HZCE t HZOE DATA VALID OHA t HZCE t HZCE Page [+] Feedback ...
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... If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high impedance state. Document #: 38-06078 Rev [31] t PWE [34] t HZWE SCE LOW CE or SEM and a LOW PWE HZWE . CY7C027V/027AV/028V CY7C037AV/038V [28, 29, 30, 31] [34] t HZOE LZWE NOTE [28, 29, 30, 36 allow the I/O drivers to turn off and data to be placed on SD PWE Page [+] Feedback ...
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... SPS Document #: 38-06078 Rev SAA VALID ADRESS SCE SOP t SD DATA VALID PWE t SWRD t SOP WRITE CYCLE READ CYCLE MATCH t SPS MATCH = HIGH. L CY7C027V/027AV/028V CY7C037AV/038V [37] t OHA t ACE DATA VALID OUT t DOE [38, 39, 40] Page [+] Feedback ...
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... Figure 11. Timing Diagram of Read with BUSY (M/S=HIGH) ADDRESS R R/W R DATA ADDRESS L BUSY L DATA OUTL Figure 12. Write Timing with Busy Input (M/S=LOW) R/W BUSY Note 41 LOW Document #: 38-06078 Rev MATCH t PWE t SD VALID MATCH t BLA t WDD t PWE CY7C027V/027AV/028V CY7C037AV/038V [41 BHA t BDD t DDD VALID Page [+] Feedback ...
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... BUSY is asserted. PS Document #: 38-06078 Rev. *D ADDRESS MATCH BLC ADDRESS MATCH BLC ADDRESS MISMATCH t t BLA BHA ADDRESS MISMATCH t t BLA BHA CY7C027V/027AV/028V CY7C037AV/038V [42] t BHC t BHC [42] Page [+] Feedback ...
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... R deasserted first 44 depends on which enable pin (CE or R/W INS INR L Document #: 38-06078 Rev. *D Figure 15. Interrupt Timing Diagrams t WC [43 READ 7FFF (FFFF for CY7C028V/38V) [44] t INR t WC [43 READ 7FFE (FFFE for CY7C028V/38V) [44] t INR ) is asserted last. L CY7C027V/027AV/028V CY7C037AV/038V Page [+] Feedback ...
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... Right port has semaphore token 1 1 Semaphore free 0 1 Left port has semaphore token 1 1 Semaphore free CY7C027V/027AV/028V CY7C037AV/038V –I/O Operation 8 Deselected: Power-down Deselected: Power-down Write to upper byte only Write to lower byte only Write to both bytes Read upper byte only Read lower byte only ...
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... Ordering Information 32K x16 3.3 V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code 15 CY7C027V-15AXC CY7C027V-15AXI 20 CY7C027V-20AC CY7C027V-20AXC 25 CY7C027V-25AC CY7C027V-25AI CY7C027V-25AXC CY7C027AV-25AXI 64K x16 3.3 V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code 15 CY7C028V-15AXC CY7C028V-15AXI 20 CY7C028V-20AC CY7C028V-20AXC CY7C028V-20AI CY7C028V-20AXI 25 CY7C028V-25AC CY7C028V-25AXC 32K x18 3.3 V Asynchronous Dual-Port SRAM ...
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... Ordering Code Definition Document #: 38-06078 Rev Operating Range C = Com m ercial I = Industrial free (RoHS Com pliant) Package: A=TQFP Speed Grade : 15ns/20ns/25ns X = V/AV : 3.3 V Depth: 7=32K or 8=64K W idth: 02=x16 or 03=x18 7C = Dual Port SRAM Com pany ID Cypress CY7C027V/027AV/028V CY7C037AV/038V Page [+] Feedback ...
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... Package Diagram Figure 16. 100-Pin Pb-Free Thin Plastic Quad Flat Pack (TQFP) A100 Document #: 38-06078 Rev. *D CY7C027V/027AV/028V CY7C037AV/038V 51-85048 *D Page [+] Feedback ...
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... Acronyms Acronym Description CMOS complementary metal oxide semiconductor TQFP thin quad plastic flatpack I/O input/output SRAM static random access memory Document #: 38-06078 Rev. *D CY7C027V/027AV/028V CY7C037AV/038V Document Conventions Units of Measure Symbol Unit of Measure ns nano seconds V Volts µA micro Amperes mA milli Amperes ...
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... Document History Page Document Title: CY7C027V/027AV/CY7C028V/037AV/038V 3.3 V 32K/64K X 16/18 DUAL PORT STATIC RAM Document Number: 38-06078 Orig. of Rev. ECN No. Change ** 237626 YDT *A 259110 JHX *B 2623540 VKN/PYRS *C 2897217 RAME *D 3093542 ADMU Document #: 38-06078 Rev. *D Submission Description of Change Date 6/30/04 Converted data sheet from old spec 38-00670 to conform with new data sheet ...
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... Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-06078 Rev. *D All products and company names mentioned in this document may be the trademarks of their respective holders. cypress.com/go/plc Revised November 25, 2010 CY7C027V/027AV/028V CY7C037AV/038V PSoC Solutions psoc.cypress.com/solutions PSoC 1 | ...