CY7C1370D-250AXCT Cypress Semiconductor Corp, CY7C1370D-250AXCT Datasheet - Page 21

• Manufacturer Part Number: CY7C1370D-250AXCT
• Description: CY7C1370D-250AXCT
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1370D-250AXCT

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 18M (512K x 36)
• Speed: 250MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Switching Characteristics
Over the Operating Range
Document Number: 38-05555 Rev. *K
t
Clock
t
F
t
t
Output Times
t
t
t
t
t
t
t
Setup Times
t
t
t
t
t
t
Hold Times
t
t
t
t
t
t
Notes
Power
CYC
CH
CL
CO
EOV
DOH
CHZ
CLZ
EOHZ
EOLZ
AS
DS
CENS
WES
ALS
CES
AH
DH
CENH
WEH
ALH
CEH
19. This part has a voltage regulator internally; t
20. t
21. At any given voltage and temperature, t
22. This parameter is sampled and not 100% tested.
23. Timing reference is 1.5V when V
24. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
MAX
Parameter
initiated.
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
CHZ
[19]
, t
CLZ
, t
EOLZ
, and t
V
Clock Cycle Time
Maximum Operating Frequency
Clock HIGH
Clock LOW
Data Output Valid After CLK Rise
OE LOW to Output Valid
Data Output Hold After CLK Rise
Clock to High-Z
Clock to Low-Z
OE HIGH to Output High-Z
OE LOW to Output Low-Z
Address Setup Before CLK Rise
Data Input Setup Before CLK Rise
CEN Setup Before CLK Rise
WE, BW
ADV/LD Setup Before CLK Rise
Chip Select Setup
Address Hold After CLK Rise
Data Input Hold After CLK Rise
CEN Hold After CLK Rise
WE, BW
ADV/LD Hold after CLK Rise
Chip Select Hold After CLK Rise
CC
(typical) to the first access read or write
EOHZ
x
x
are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
Setup Before CLK Rise
Hold After CLK Rise
[23, 24]
DDQ
[20, 21, 22]
Description
[20, 21, 22]
= 3.3V and is 1.25V when V
EOHZ
Power
is less than t
is the time power needs to be supplied above V
[20, 21, 22]
[20, 21, 22]
EOLZ
and t
DDQ
CHZ
= 2.5V.
is less than t
Min
4.0
1.7
1.7
1.0
1.0
1.2
1.2
1.2
1.2
0.3
0.3
0.3
0.3
0.3
0.3
1.2
1.2
1
0
–250
CLZ
to eliminate bus contention between SRAMs when sharing the same
Max
250
2.6
2.6
2.6
2.6
DD
minimum initially, before a Read or Write operation can be
Min
2.0
2.0
1.3
1.4
1.4
0.4
0.4
0.4
0.4
1.3
1.4
1.4
1.4
1.4
0.4
0.4
1
5
0
–200
CY7C1370D, CY7C1372D
Max
200
3.0
3.0
3.0
3.0
Min
2.2
2.2
1.3
1.3
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
1
6
0
–167
Max
167
3.4
3.4
3.4
3.4
Page 21 of 29
MHz
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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