CY7C1470V25-200BZI Cypress Semiconductor Corp, CY7C1470V25-200BZI Datasheet

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... Pb-free and non Pb-free 209-ball FBGA package IEEE 1149.1 JTAG boundary scan compatible ■ Burst capability—linear or interleaved burst order ■ “ZZ” sleep mode option and stop clock option ■ Logic Block Diagram - CY7C1470V25 (2 M × 36) A0, A1, A REGISTER 0 MODE CLK C CEN ...

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... ARRAY CONTROL LOGIC DRIVERS INPUT REGISTER 1 READ LOGIC Sleep Control ADDRESS REGISTER BURST A0 LOGIC ADV/LD C WRITE ADDRESS REGISTER 2 WRITE REGISTRY MEMORY AND DATA COHERENCY WRITE ARRAY CONTROL LOGIC DRIVERS INPUT REGISTER 1 READ LOGIC Sleep Control CY7C1470V25 CY7C1472V25 CY7C1474V25 DQs DQP T a ...

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... TAP Timing ...................................................................... 14 TAP AC Switching Characteristics ............................... 14 2.5 V TAP AC Test Conditions ....................................... 15 2.5 V TAP AC Output Load Equivalent ......................... 15 1.8 V TAP AC Test Conditions ....................................... 15 1.8 V TAP AC Output Load Equivalent ........................ 15 Document Number: 38-05290 Rev. *L CY7C1470V25 CY7C1472V25 CY7C1474V25 TAP DC Electrical Characteristics and Operating Conditions ..................................................... 15 Identification Register Definitions ................................ 15 Scan Register Sizes ....................................................... 16 Identification Codes ....................................................... 16 Boundary Scan Exit Order (2 M × ...

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... DQa 18 63 DQa DQb DDQ 61 DDQ DQa DQb 22 59 DQa DQb 23 58 DQa DQPb 24 57 DQa DDQ 54 DDQ DQa DQa DQPa CY7C1470V25 CY7C1472V25 CY7C1474V25 167 MHz Unit 3.4 ns 400 mA 120 DDQ DQPa 74 DQa 73 DQa DDQ DQa 69 DQa DQa 63 DQa DDQ V 60 ...

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... DDQ DDQ DDQ N DQP DDQ P NC/144M MODE NC/576M NC/1G A CE2 DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ N DQP DDQ P NC/144M MODE A A Document Number: 38-05290 Rev. *L CY7C1470V25 (2 M × 36 CEN CLK TDI A1 TDO TCK TMS CY7C1472V25 (4 M × 18 ...

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... DDQ MODE TDI Pin Description controls DQ a and DQP , BW controls DQ and DQP and DQP BW controls DQ and DQP CY7C1470V25 CY7C1472V25 CY7C1474V25 DQb DQb 3 BWS DQb DQb b f BWS DQb DQb DQb DQb DQPf DQPb DDQ DDQ V DQf V DQf DQf DQf DDQ DDQ ...

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... The direction of the pins is [18:0] –DQ are placed in a tri-state condition. The outputs are controlled DQP is controlled controlled DQP is controlled DQP is controlled CY7C1470V25 CY7C1472V25 CY7C1474V25 . During [71:0] , DQP is controlled DQP is controlled Page [+] Feedback ...

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... Byte write capability has been included in order to greatly simplify CY7C1470V25 CY7C1472V25 CY7C1474V25 Single Read /DQP for CY7C1474V25, a,b,c,d,e,f,g,h for CY7C1470V25 and DQ /DQP a,b,c,d a,b /DQP for CY7C1474V25, a,b,c,d,e,f,g,h for CY7C1470V25 & DQ /DQP a,b,c,d a,b for CY7C1474V25, BW for CY7C1470V25 a,b,c,d for CY7C1472V25) signals. unaltered. A synchronous self-timed Page ...

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... CY7C1472V25) are automatically tri-stated during the data portion of a write cycle, regardless of the state of OE. Burst Write Accesses The CY7C1470V25/CY7C1472V25/CY7C1474V25 has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four write operations without reasserting the address inputs. ADV/LD must be driven LOW in ...

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... Next NOP/write abort (begin burst) None Write abort (continue burst) Next Ignore clock edge (stall) Current Sleep mode None Partial Write Cycle Description Function (CY7C1470V25) Read Write – no bytes written Write byte a – (DQ and DQP ) a a Write byte b – (DQ and DQP ...

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... Write – no bytes written Write byte a – (DQ and DQP ) a a Write byte b – (DQ and DQP ) b b Write both bytes Function (CY7C1474V25) Read Write – no bytes written Write byte X(DQ and DQP x x) Write all bytes Document Number: 38-05290 Rev. *L CY7C1470V25 CY7C1472V25 CY7C1474V25 ...

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... TAPs. The TAP operates using JEDEC-standard 2 1.8 V I/O logic levels. The CY7C1470V25/CY7C1472V25/CY7C1474V25 contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature ...

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... TAP controller’s capture set-up plus hold time (t plus The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue still CY7C1470V25 CY7C1472V25 CY7C1474V25 Page [+] Feedback ...

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... Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions CYC TL t TMSS t TMSH t TDIS t TDIH t TDOX DON’T CARE UNDEFINED Description / ns CY7C1470V25 CY7C1472V25 CY7C1474V25 TDOV Min Max Unit 50 – ns – 20 MHz 20 – – ns – ...

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... I DDQ CY7C1472V25 CY7C1474V25 (4 M × 18 × 72) 000 000 000 01011 01011 01011 001000 001000 001000 100100 010100 110100 00000110100 00000110100 CY7C1470V25 CY7C1472V25 CY7C1474V25 – 0.2 DDQ 0.9V 50 50 20pF O Min Max Unit 1.7 – V 2.1 – V 1.6 – V – 0.4 V – ...

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... Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. Document Number: 38-05290 Rev. *L Bit Size (× 36) Bit Size (× 18 – – Description CY7C1470V25 CY7C1472V25 CY7C1474V25 Bit Size (× 72 – 110 Page [+] Feedback ...

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... K11 60 165-ball ID Bit # P10 R10 37 25 R11 38 26 M10 39 CY7C1470V25 CY7C1472V25 CY7C1474V25 165-ball ID Bit # 165-ball ID J11 61 B7 K10 62 B6 J10 63 A6 H11 64 B5 G11 65 A5 F11 66 A4 E11 67 B4 D10 68 B3 D11 69 A3 C11 70 A2 G10 71 B2 F10 E10 A9 B9 A10 ...

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... J11 V5 72 J10 U5 73 H11 U6 74 H10 W7 75 G11 V7 76 G10 U7 77 F11 V8 78 F10 V9 79 E10 W11 80 E11 W10 81 D11 V11 82 D10 V10 83 C11 U11 84 C10 CY7C1470V25 CY7C1472V25 CY7C1474V25 Bit # 209-ball ID 85 B11 86 B10 87 A11 88 A10 100 B3 101 C3 102 C4 103 ...

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... All speed grades DD  0 0 > DDQ /2), undershoot: V (AC) > –2 V (Pulse width less than t CYC IL (min) within 200 ms. During this time V < V and CY7C1470V25 CY7C1472V25 CY7C1474V25 Ambient DDQ Temperature 2.5 V – 1 –40 °C to +85 °C Min Max Unit 2.375 2.625 2.375 ...

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... MHz 2 2.5 V DDQ 100 TQFP Test Conditions Package Test conditions follow standard 24.63 test methods and procedures for measuring thermal impedance, 2.28 per EIA/JESD51. CY7C1470V25 CY7C1472V25 CY7C1474V25 Min Max Unit – 200 mA – 200 mA – 200 mA – 135 mA 165 FBGA ...

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... Document Number: 38-05290 Rev 1667  2 DDQ GND 1538  INCLUDING JIG AND (b) SCOPE K 1 0.2 DDQ 0 K INCLUDING JIG AND (b) SCOPE CY7C1470V25 CY7C1472V25 CY7C1474V25 ALL INPUT PULSES 90% 90% 10% 10%   (c) ALL INPUT PULSES 90% 90% 10% 10%   (c) Page [+] Feedback ...

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... V minimum initially, before a read or write operation can be DD and t is less than t to eliminate bus contention between SRAMs when sharing the same EOLZ CHZ CLZ CY7C1470V25 CY7C1472V25 CY7C1474V25 –200 –167 Unit Min Max Min ...

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... DOH CLZ D(A1) D(A2) D(A2+1) Q(A3) t BURST READ READ BURST WRITE Q(A3) Q(A4) READ D(A2+1) Q(A4+1) DON’T CARE UNDEFINED is LOW. When CE is HIGH,CE is HIGH CY7C1470V25 CY7C1472V25 CY7C1474V25 OEV CHZ Q(A4) Q(A4+1) D(A5) Q(A6) OEHZ t DOH t OELZ WRITE READ WRITE ...

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... A4 D(A1) Q(A2) Q(A3) STALL READ WRITE STALL Q(A3) D(A4) DON’T CARE ZZI I DDZZ High-Z DON’T CARE is LOW. When CE is HIGH,CE is HIGH CY7C1470V25 CY7C1472V25 CY7C1474V25 CHZ D(A4) Q(A5) NOP READ DESELECT CONTINUE Q(A5) DESELECT UNDEFINED t ZZREC t RZZI DESELECT or READ Only is LOW HIGH ...

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... CY7C1470V25-200BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 × 17 × 1.4mm) Pb-free CY7C1474V25-200BGC 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) CY7C1470V25-200BZI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 × 17 × 1.4mm) CY7C1474V25-200BGI 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) CY7C1474V25-200BGXI 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × ...

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... Package Diagrams Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm), 51-85050 Figure 2. 165-ball FBGA (15 × 17 × 1.4 mm), 51-85165 Document Number: 38-05290 Rev. *L CY7C1470V25 CY7C1472V25 CY7C1474V25 51-85050 *D 51-85165 *B Page [+] Feedback ...

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... Figure 3. 209-ball FPBGA (14 × 22 × 1.76 mm), 51-85167 Document Number: 38-05290 Rev. *L CY7C1470V25 CY7C1472V25 CY7C1474V25 51-85167 *A Page [+] Feedback ...

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... TDI test data input TMS test mode select TDO test data output TQFP thin quad flat pack WE write enable Document Number: 38-05290 Rev. *L CY7C1470V25 CY7C1472V25 CY7C1474V25 Document Conventions Units of Measure Symbol Unit of Measure ns nano seconds V Volts µA micro Amperes ...

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... Document History Page Document Title: CY7C1470V25/CY7C1472V25/CY7C1474V25 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBL™ Architecture Document Number: 38-05290 Orig. of REV. ECN No. Issue Date Change ** 114677 08/06/02 PKS *A 121519 01/27/03 CJM *B 223721 See ECN NJY *C 235012 See ECN ...

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... Document History Page (continued) Document Title: CY7C1470V25/CY7C1472V25/CY7C1474V25 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBL™ Architecture Document Number: 38-05290 *I 472335 See ECN VKN *J 2898958 03/25/10 NJY *K 3054137 10/10/2010 NJY *L 3207715 03/28/2011 NJY Document Number: 38-05290 Rev. *L Corrected the typo in the pin configuration for 209-Ball FBGA pinout ...

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... Document Number: 38-05290 Rev. *L NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology, Inc. All products and company names mentioned in this document may be the trademarks of their respective holders. cypress.com/go/plc Revised March 28, 2011 CY7C1470V25 CY7C1472V25 CY7C1474V25 PSoC Solutions psoc.cypress.com/solutions ...