CY8C3246PVI-141 Cypress Semiconductor Corp, CY8C3246PVI-141 Datasheet - Page 63

• Manufacturer Part Number: CY8C3246PVI-141
• Description: CY8C3246PVI-141
• Manufacturer: Cypress Semiconductor Corp
• Series: PSOC™ 3 CY8C32xxr

Specifications of CY8C3246PVI-141

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, LIN, SPI, UART/USART
• Peripherals: CapSense, DMA, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 5.5 V
• Data Converters: A/D 2x12b, D/A 1x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.2 Device Level Specifications
Specifications are valid for –40 °C ≤ T
except where noted.
11.2.1 Device Level Specifications
Table 11-2. DC Specifications
Document Number: 001-56955 Rev. *J
V
V
V
V
V
V
V
I
Notes
Parameter
DD
16. The power supplies can be brought up in any sequence however once stable V
17. The V
18. The current consumption of additional peripherals that are implemented only in programmed logic blocks can be found in their respective datasheets, available in
DDA
DDA
DDD
DDD
DDIO
CCA
CCD
[18]
PSoC Creator, the integrated design environment. To estimate total current, find CPU current at frequency of interest and add peripheral currents for your particular
system from the device datasheet and component datasheets.
[17]
DDIO
supply voltage must be greater than the maximum analog voltage on the associated GPIO pins. Maximum analog voltage on GPIO pin ≤ V
Analog supply voltage and input to
analog core regulator
Analog supply voltage, analog
regulator bypassed
Digital supply voltage relative to
V
Digital supply voltage, digital
regulator bypassed
I/IO supply voltage relative to V
Direct analog core voltage input
(Analog regulator bypass)
Direct digital core voltage input
(Digital regulator bypass)
Active Mode, V
Bus clock off. Execute from CPU
instruction buffer. See
Program Memory”
V
clock enabled, ILO = 1 kHz, CPU
executing from flash and accessing
SRAM, all other blocks off, all I/Os
tied low.
SSD
DD
= 3.3 V, T = 25 °C, IMO and bus
Description
DD
on page 22.
= 1.71 V–5.5 V
“Flash
A
≤ 85 °C and T
SSIO
Analog core regulator enabled
Analog core regulator disabled
Digital core regulator enabled
Digital core regulator disabled
Analog core regulator disabled
Digital core regulator disabled
CPU at 3 MHz
CPU at 6 MHz
CPU at 12 MHz
CPU at 24 MHz
CPU at 48 MHz
CPU at 3 MHz
CPU at 6 MHz
CPU at 12 MHz
CPU at 24 MHz
CPU at 48 MHz
J
≤ 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,
Conditions
DDA
must be greater than or equal to all other supplies.
T = –40 °C
T = 25 °C
T = 85 °C
T = –40 °C
T = 25 °C
T = 85 °C
T = –40 °C
T = 25 °C
T = 85 °C
T = –40 °C
T = 25 °C
T = 85 °C
T = –40 °C
T = 25 °C
T = 85 °C
PSoC
1.71
1.71
1.71
1.71
1.71
Min
1.8
1.8
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
®
3: CY8C32 Family
11.8
Typ
1.8
1.8
1.8
1.8
0.8
1.2
2.0
3.5
6.6
1.4
2.2
3.6
6.4
–
–
–
–
–
–
–
–
–
–
–
–
–
Data Sheet
V
V
DDA
DDA
Max
1.89
1.89
1.89
1.89
5.5
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Page 63 of 119
[16]
[16]
DDIO
Units
≤ V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
V
V
V
V
V
V
V
DDA
.
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