DSPIC33FJ12MC202-E/SP Microchip Technology, DSPIC33FJ12MC202-E/SP Datasheet - Page 68

• Manufacturer Part Number: DSPIC33FJ12MC202-E/SP
• Description: 12KB, Flash, 1024bytes-RAM, 40MIPS, 21I/O, 16-bit Family,nanoWatt,MotorControl 2
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ12MC202-E/SP

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164337 - MODULE SOCKET FOR PM3 40DIP
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

dsPIC33FJ12MC201/202
6.9.0.1
A device Reset is generated if the device attempts to
execute an illegal opcode value that is fetched from
program memory.
The illegal opcode Reset function can prevent the
device from executing program memory sections that
are used to store constant data. To take advantage of
the illegal opcode Reset, use only the lower 16 bits of
each program memory section to store the data values.
The upper 8 bits should be programmed with 3Fh,
which is an illegal opcode value.
6.9.0.2
Any attempts to use the uninitialized W register as an
address pointer will Reset the device. The W register
array (with the exception of W15) is cleared during all
Resets and is considered uninitialized until written to.
6.9.0.3
If a Program Flow Change (PFC) or Vector Flow
Change (VFC) targets a restricted location in a
protected segment (Boot and Secure Segment), that
operation will cause a security Reset.
The PFC occurs when the Program Counter is
reloaded as a result of a Call, Jump, Computed Jump,
Return, Return from Subroutine, or other form of
branch instruction.
The VFC occurs when the Program Counter is
reloaded with an Interrupt or Trap vector.
Refer to Section 21.8 “Code Protection and
CodeGuard™ Security” for more information on
Security Reset.
TABLE 6-3:
DS70265D-page 66
TRAPR (RCON<15>)
IOPWR (RCON<14>)
CM (RCON<9>)
EXTR (RCON<7>)
SWR (RCON<6>)
WDTO (RCON<4>)
SLEEP (RCON<3>)
IDLE (RCON<2>)
BOR (RCON<1>)
POR (RCON<0>)
Note: All Reset flag bits can be set or cleared by user software.
ILLEGAL OPCODE RESET
UNINITIALIZED W REGISTER
RESET
SECURITY RESET
Flag Bit
RESET FLAG BIT OPERATION
Trap conflict event
Illegal opcode or uninitialized
W register access or Security Reset
Configuration Mismatch
MCLR Reset
RESET instruction
WDT Time-out
PWRSAV #SLEEP instruction
PWRSAV #IDLE instruction
POR, BOR
POR
Preliminary
Set by:
6.10
The user application can read the Reset Control
(RCON) register after any device Reset to determine
the cause of the Reset.
Table 6-3 provides a summary of Reset flag bit
operation.
Note:
Using the RCON Status Bits
The status bits in the RCON register
should be cleared after they are read so
that the next RCON register value after a
device Reset will be meaningful.
POR, BOR
POR, BOR
POR, BOR
POR, BOR
POR, BOR
POR, BOR
POR
PWRSAV instruction,
CLRWDT instruction, POR, BOR
© 2009 Microchip Technology Inc.
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