FM24C64B-GTR Ramtron, FM24C64B-GTR Datasheet - Page 7

• Manufacturer Part Number: FM24C64B-GTR
• Description: SOIC8 T&R
• Manufacturer: Ramtron

master issues a start condition. This simultaneously
aborts the write operation and allows the read
command to be issued with the device address LSB
Endurance
The FM24C64B internally operates with a read and
restore mechanism. Therefore, endurance cycles are
applied for each read or write cycle. The memory
architecture is based on an array of rows and
columns. Each read or write access causes an
endurance cycle for an entire row. In the FM24C64B,
a row is 64 bits wide. Every 8-byte boundary marks
Rev. 1.3
Feb. 2011
By FM24C64B
By Master
By FM24C64B
By Master
Start
S
Slave Address
By FM24C64B
By Master
Start
S
0
A
Slave Address
X
Start
Address
S
Address MSB
Address
Figure 9. Selective (Random) Read
Slave Address
Figure 7. Current Address Read
Acknowledge
Address
1
Figure 8. Sequential Read
A
A
Acknowledge
Address LSB
Acknowledge
Data Byte
1
A
set to a 1. The operation is now a current address
read.
the beginning of a new row. Endurance can be
optimized by ensuring frequently accessed data is
located in different rows. Regardless, FRAM read
and write endurance is effectively unlimited at the
1MHz two-wire speed. Even at 3000 accesses per
second to the same segment, 10 years time will
elapse before 1 trillion endurance cycles occur.
Acknowledge
Data Byte
A
Data
Start
S
A
Data
Slave Address
Acknowledge
Address
Data Byte
No
1
P
1
Acknowledge
A
No
1 P
Stop
Data Byte
Data
Acknowledge
FM24C64B
Stop
No
1 P
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Stop