LTC2442IG Linear Technology, LTC2442IG Datasheet - Page 17

• Manufacturer Part Number: LTC2442IG
• Description: IC,A/D CONVERTER,SINGLE,24-BIT,CMOS,SSOP,36PIN
• Manufacturer: Linear Technology

As described above, CS may be pulled LOW at any time in
order to monitor the conversion status on the SDO pin.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pull-
ing CS HIGH anytime between the fi fth falling edge and
the 32nd falling edge of SCK, see Figure 5. On the rising
edge of CS, the device aborts the data output state and
immediately initiates a new conversion. Thirteen serial
input data bits are required in order to properly program
the speed/resolution and input channel. If the data output
APPLICATIO S I FOR ATIO
CONVERSION
(EXTERNAL)
BUSY
SDO
SCK
SDI
CS
U
SLEEP
U
1
DATA OUTPUT
DON'T CARE
Figure 5. External Serial Clock, Reduced Output Data Length
5
0.1V TO V
REFERENCE
ANALOG
W
INPUTS
VOLTAGE
0.1µF
0.1µF
1µF
4.5V TO 5.5V
CONVERSION
CC
Hi-Z
29
30
31
28
12
13
11
17
18
10
6
7
8
9
V
REF
REF
CH0
CH1
CH2
CH3
COM
OUTA
–INA
ADCINA
OUTB
–INB
ADCINB
CC
U
1
BIT 31
EOC
+
–
LTC2442
MUXOUTA
MUXOUTB
2
BIT 30
“0”
BUSY
+INA
+INB
GND
SDO
SCK
EXT
SDI
CS
V
F
V
O
3
+
–
DON'T CARE
BIT 29
SIG
V
21
27
25
26
19
24
4, 5, 32
CC
DATA OUTPUT
33
36
35
34
3
1
2
sequence is aborted prior to the 13th rising edge of SCK,
the new input data is ignored, and the previously selected
speed/resolution and channel are used for the next conver-
sion cycle. This is useful for systems not requiring all 32
bits of output data, aborting an invalid conversion cycle or
synchronizing the start of a conversion. If a new channel
is being programmed, the rising edge of CS must come
after the 14th falling edge of SCK in order to store the
data input sequence.
TO 15V
4
BIT 28 BIT 27 BIT 26 BIT 25
–15V TO GND
MSB
1µF
4-WIRE
SPI INTERFACE
5
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
(SIMULTANEOUS 50Hz/60Hz
REJECTION AT 6.9Hz OUTPUT RATE
6
Hi-Z
CONVERSION
TEST EOC
DON'T CARE
LTC2442
SLEEP
2442 F05
17
2442f