LTC4253AIGN Linear Technology, LTC4253AIGN Datasheet - Page 12

• Manufacturer Part Number: LTC4253AIGN
• Description: MS-Hot Swap/High Voltage, Neg. 48V Hot Swap With 1% UV, Sequencer
• Manufacturer: Linear Technology

Specifications of LTC4253AIGN

• Family Name: LTC4253A
• Package Type: SSOP N
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 3.99mm
• Product Height (mm): 1.5mm
• Mounting: Surface Mount
• Pin Count: 16
• Lead Free Status / Rohs Status: Not Compliant

OPERATIO
LTC4253/LTC4253A
Interlock Conditions
A start-up sequence commences once these “interlock”
conditions are met:
1. The input voltage V
2. The voltage at UV > V
3. The voltage at OV < V
4. The input voltage at RESET < 0.8V.
5. The (SENSE – V
6. The voltage at SS is < 0.2V (20 • V
7. The voltage on the TIMER capacitor (C
8. The voltage at GATE is < 0.5V (V
The first four conditions are continuously monitored and
the latter four are checked prior to initial timing or GATE
ramp-up. Upon exiting an OV condition, the TIMER pin
voltage requirement is inhibited. Details are described in
the Applications Information, Timing Waveforms section.
If RESET < 0.8V occurs after the LTC4253/LTC4253A
come out of UVLO (interlock condition 1) and undervoltage
(interlock condition 2), GATE and SS are released without
an initial TIMER cycle once the other interlock conditions
are met (see Figure 13a). If not, TIMER begins the start-up
sequence by sourcing 5µA into C
of range or RESET asserts, the start-up cycle stops and
TIMER discharges C
aforementioned conditions are once again met. If C
successfully charges to 4V, TIMER pulls low and both SS
and GATE pins are released. GATE sources 50µA (I
charging the MOSFET gate and associated capacitance.
The SS voltage ramp limits V
current. PWRGD1 pulls active low when GATE is within
2.8V of V
the power good sequence in which PWRGD2 and then
PWRGD3 is subsequently pulled low after a delay, adjust-
able through the SQTIMER capacitor C
control inputs EN2 and EN3. In this way, external loads or
power modules controlled by the three PWRGD signals
are turned on in a controlled manner without overloading
the power bus.
12
LTC4253A).
is < 1V (V
IN
and DRAIN is lower than V
TMRL
).
U
EE
T
) voltage < 50mV (V
to less than 1V, then waits until the
IN
UVHI
exceeds V
OVLO
(V
SENSE
UV
T
(V
. If V
for the LTC4253A).
LKO
OV
GATEL
to control the inrush
IN
OS
DRNL
– V
(UVLO).
, UV or OV falls out
SQ
)
)
CB
T
OVHST
)
or by external
. This sets off
)
for the
GATE
),
T
Two modes of operation are possible during the time the
MOSFET is first turned on, depending on the values of
external components, MOSFET characteristics and nomi-
nal design current. One possibility is that the MOSFET will
turn on gradually so that the inrush into the load capaci-
tance remains a low value. The output will simply ramp to
– 48V and the LTC4253/LTC4253A will fully enhance the
MOSFET. A second possibility is that the load current
exceeds the soft-start current limit threshold of [V
20 – V
the output by sourcing soft-start limited current into the
load capacitance. If the soft-start voltage is below 1.2V,
the circuit breaker TIMER is held low. Above 1.2V, TIMER
ramps up. It is important to set the timer delay so that,
regardless of which start-up mode is used, the TIMER
ramp is less than one circuit breaker delay time. If this
condition is not met, the LTC4253/LTC4253A may shut
down after one circuit breaker delay time.
Board Removal
When the board is withdrawn from the card cage, the
UV/OV divider is the first to lose connection. This shuts off
the MOSFET and commutates the flow of current in the
connector. When the power pins subsequently separate
there is no arcing.
Current Control
Three levels of protection handle short-circuit and over-
load conditions. Load current is monitored by SENSE and
resistor R
50mV for a timed circuit breaker function; 100mV for an
analog current limit loop (60mV for the LTC4253A); and
200mV for a fast, feedforward comparator which limits
peak current in the event of a catastrophic short-circuit.
If, due to an output overload, the voltage drop across R
exceeds 50mV, TIMER sources 200µA into C
ally charges to a 4V threshold and the LTC4253/LTC4253A
shut off. If the overload goes away before C
and SENSE measures less than 50mV, C
charges (5µA). In this way the LTC4253/LTC4253A’s
circuit breaker function responds to low duty cycle over-
loads, and accounts for the fast heating and slow cooling
characteristic of the MOSFET.
OS
]/R
S
. There are three distinct thresholds at SENSE:
S
. In this case the LTC4253/LTC4253A ramp
T
T
T
. C
slowly dis-
reaches 4V
T
eventu-
425353afc
SS
(t)/
S