WM8350GEB/V Wolfson Microelectronics, WM8350GEB/V Datasheet - Page 139

• Manufacturer Part Number: WM8350GEB/V
• Description: Audio CODECs Audio CODEC plus pwr management
• Manufacturer: Wolfson Microelectronics

Specifications of WM8350GEB/V

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Production Data
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The LDO Regulators can also be controlled by the device HIBERNATE bit, or by hardware input
signals L_PWR1, L_PWR2 and L_PWR3. Several GPIO pins can be assigned as L_PWR pins. Each
Regulator can be assigned to one of these three signals, or else to the device HIBERNATE bit. The
signals are active high and each Regulator’s response to the selected signal is programmable as
defined in Table 83.
Note that, when a GPIO pin is configured as a Hibernate input pin, and this input is asserted, then all
LDO Regulators will be placed in Hibernate mode.
In order to use GPIO pins as L_PWR pins, they must be configured by setting the respective
GPn_FN, and GPn_DIR bits to the appropriate value (see Section 20).
R202 (CAh)
for LDO1
R205 (CDh)
for LDO2
R208 (D0h)
for LDO3
R211 (D3h)
for LDO4
Note: n is a number between 1 and 4 that identifies the individual LDO regulator
Table 83 Configuring Hardware Control for LDO Regulators
When the LDO Regulators are disabled, the output can be set to float or else the outputs can be
actively discharged through internal resistors. This feature is controlled using the register bits
described in Table 84.
Note that the “float” option is only supported when at least one other LDO Regulator remains
enabled. If LDO Regulators 1, 2, 3 and 4 are all disabled, then the LDO Regulator outputs will be
discharged, regardless of the LDOn_OPFLT registers.
R200 (C8h)
for LDO1
R203 (CBh)
for LDO2
R206 (CEh)
for LDO3
R209 (D1h)
for LDO4
Note: n is a number between 1 and 4 that identifies the individual LDO regulator
Table 84 Output Float Control for LDO Regulators
ADDRESS
ADDRESS
13:12
BIT
10
BIT
9:8
LDOn_OPFLT
LDOn_HIB_M
ODE [1:0]
LDOn_HIB_T
RIG [1:0]
LABEL
LABEL
DEFAULT
DEFAULT
00
00
0
LDOn Hibernate behaviour:
00 = Select voltage image settings
01 = disable output
10 = reserved
11 = reserved
LDOn Hibernate signal select
00 = Hibernate register bit
01 = L_PWR1
10 = L_PWR2
11 = L_PWR3
Enable discharge of LDOn outputs
when LDOn is disabled
0 = Enabled - Output to be discharged
1 = Disabled - Output is left floating
Note - if LDO Regulators 1, 2, 3 and 4
are all disabled, then the outputs will all
be discharged, regardless of the
LDOn_OPFLT bit.
DESCRIPTION
DESCRIPTION
PD, March 2010, Rev 4.2
WM8350
139