CS42418-CQZR Cirrus Logic Inc, CS42418-CQZR Datasheet - Page 48

Audio CODECs IC 192kHz 110dB 6Ch Multi-Ch CODEC

CS42418-CQZR

Manufacturer Part Number
CS42418-CQZR
Description
Audio CODECs IC 192kHz 110dB 6Ch Multi-Ch CODEC
Manufacturer
Cirrus Logic Inc
Datasheet

Specifications of CS42418-CQZR

Number Of Adc Inputs
2
Number Of Dac Outputs
8
Conversion Rate
192 KSPs
Interface Type
Serial (I2C, SPI)
Resolution
24 bit
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Package / Case
LQFP-64
Minimum Operating Temperature
- 10 C
Number Of Channels
2 ADC, 8 DAC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Manufacturer:
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Quantity:
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48
6.7
6.7.1
6.7.2
6.7.3
RMCK_DIV1
7
Clock Control (address 06h)
RMCK DIVIDE (RMCK_DIVX)
OMCK FREQUENCY (OMCK FREQX)
PLL LOCK TO LRCK (PLL_LRCK)
Default = 00
Function:
Default = 00
Function:
Default = 0
0 - Disabled
1 - Enabled
Function:
When enabled, the internal PLL of the CS42418 will lock to the ADC_LRCK of the ADC serial port
(ADC_LRCK) while the ADC_SP is in Slave Mode.
Divides/multiplies the internal MCLK, either from the PLL or OMCK, by the selected factor.
Sets the appropriate frequency for the supplied OMCK.
RMCK_DIV0
OMCK Freq1 OMCK Freq0
6
0
0
1
1
OMCK Freq1
RMCK_DIV1 RMCK_DIV0
5
0
0
1
1
Table 10. OMCK Frequency Settings
0
1
0
1
Table 9. RMCK Divider Settings
OMCK Freq0
11.2896 MHz or 12.2880 MHz
16.9344 MHz or 18.4320 MHz
22.5792 MHz or 24.5760 MHz
Reserved
4
0
1
0
1
PLL_LRCK
Description
Multiply by 2
Divide by 1
Divide by 2
Divide by 4
3
Description
SW_CTRL1
2
SW_CTRL0
1
FRC_PLL_LK
CS42418
DS603F1
0

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