CS4221-KSR Cirrus Logic Inc, CS4221-KSR Datasheet
CS4221-KSR
Specifications of CS4221-KSR
Related parts for CS4221-KSR
CS4221-KSR Summary of contents
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... V power supply, and features low power con- sumption. Selectable de-emphasis filter for 32, 44.1, and 48 kHz sample rates is also included. The CS4221 also includes an analog volume control ca- pable of 113.5 dB attenuation in 0.5 dB steps. The analog volume control architecture preserves dynamic range during attenuation. Volume control changes are implemented using a “ ...
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... CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 4 ANALOG CHARACTERISTICS ............................................................................................... 4 ABSOLUTE MAXIMUM RATINGS .......................................................................................... 6 RECOMMENDED OPERATING CONDITIONS ...................................................................... 6 SWITCHING CHARACTERISTICS ......................................................................................... 7 SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE (CS4221) .................... 8 SWITCHING CHARACTERISTICS - CONTROL PORT - I 2. TYPICAL CONNECTION DIAGRAM — CS4220 ................................................................... 10 3. TYPICAL CONNECTION DIAGRAM — CS4221 ................................................................... 11 4. REGISTER QUICK REFERENCE - CS4221 .......................................................................... 12 5 ...
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... Figure 2. SPI Control Port Timing ................................................................................................. 8 2 Figure Control Port Timing .................................................................................................. 9 Figure 4. CS4220 Recommended Connection Diagram ............................................................. 10 Figure 5. CS4221 Recommended Connection Diagram ............................................................. 11 Figure 6. Control Port Timing, SPI mode .................................................................................... 24 Figure 7. Control Port Timing, I Figure 8. Serial Audio Format 0 (I2S) ......................................................................................... 25 Figure 9. Serial Audio Format 1 .................................................................................................. 25 Figure 10. Serial Audio Format 2 ................................................................................................ 25 Figure 11 ...
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... C; VA Full Scale Input Sine wave, 997 Hz; A Symbol THD A-weighted unweighted (Note 1) THD+N (1 kHz) with High Pass Filter (Note 2) (Note 2) (Note (Note (Note 2) (Note 2) = 15/48 kHz = 312 µs. gd CS4220 CS4221 CS4220 Min Typ Max Unit - - 24 - 0.003 - 95 100 - -92 -87 ...
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... Symbol (CS4221 only) DAC muted, A-weighted DAC not muted, A-weighted DAC not muted, unweighted THD THD+N (1 kHz) All Outputs Resistance Capacitance (Notes 5 and 6) (Note 6) (Notes 5 and 6) (Note Total Power Down 1 kHz CS4220 CS4221 CS4220 Min Typ Max - - 97 105 95 100 0.003 - -92 - 0.1 ...
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... Digital Inputs (AGND, DGND = 0 V, all voltages with respect to 0 V.) Symbol Digital VD Analog VA (Note 8) (Note 9) (Note 9) Power Applied Symbol Min Digital VD 4.75 Analog VA 4.75 Digital CS4220 CS4221 Min Max Unit 2 0 0.3 V -0 µ µA Min Max Unit -0.3 6 ...
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... XTI = 384 Fs XTI = 256 Fs (Note 10) DSCK = 0 t dpd t lrpd DSCK = 0 t DSCK = sckw t sckh t sckl DSCK = 0 t lrckd DSCK = 0 t lrcks lrckd lrcks sckh lrpd ds dh MSB Figure 1. Serial Audio Port Data I/O Timing CS4220 CS4221 Min Typ Max 1.024 - 500 - --------------------- - ...
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... SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE (CS4221 25° 5.25 V; Inputs: Logic 0 = DGND, Logic Parameter SPI Mode (SPI/I2C = 0) CCLK Clock Frequency RST rising edge to CS falling CCLK edge to CS falling CS High Time between transmissions CS falling to CCLK edge CCLK Low Time ...
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... Repeated Start t high t hdst sud t sust low hdd 2 Figure Control Port Timing CS4220 CS4221 2 C MODE (CS4221 pF) L Min Max - 100 50 - 4.7 - 4.0 - 4.7 - 4 250 - - 300 4.7 - Stop susp hdst ...
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... SCLK NC 4 LRCK SDIN 8 NC SDOUT AGND DGND 22 7 (Also see Recommended Layout Diagram ) CS4220 CS4221 0.1 µ µF Analog Filter Analog Filter Digital Audio Source External Clock Input Eliminate the crystal and capacitors when using an external clock input Audio ...
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... TYPICAL CONNECTION DIAGRAM — CS4221 Ferrite Bead +5V Supply + 1 µF 150 2.2 nF 150 150 2.2 nF 150 Microcontroller R = 500 s * Required for Master Mode only Figure 5. CS4221 Recommended Connection Diagram DS284PP3 2 0.1 µ AINL+ AOUTL+ 26 AOUTL AINL- AOUTR+ 23 AOUTR- 17 AINR+ CS4221 16 AINR- 3 XTI 2 XTO ...
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... REGISTER QUICK REFERENCE - CS4221 Addr Function 0h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved default 1h ADC Control PDN default 2h DAC Control Reserved default 3h-4h Output Attenuator ATT7 Level default 5h DSP Port Mode Reserved default 6h Converter Status ACCR Report default 7h Master Clock Con- ...
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... REGISTER DESCRIPTIONS - CS4221 Note: All registers are read/write in I 5.1 ADC Control (address 01h PDN HPDR 0 0 5.1.1 POWER DOWN ADC (PDN) Default = Disabled 1 - Enabled Function: The ADC will enter a low-power state when this function is enabled. 5.1.2 LEFT AND RIGHT CHANNEL HIGH PASS FILTER DEFEAT (HPDR-HPDL) ...
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... Zero crossing is independently monitored and implemented for each channel. The ACCR and ACCL bits in the Converter Status Report register indicate when a level change has occurred for the right and left channel MUTL SOFT CS4220 CS4221 2 1 Reserved RMP1 RMP0 0 0 DS284PP3 0 0 ...
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... DAC output. Binary Code 00000000 11100011 11100100 DS284PP3 ATT5 ATT4 ATT3 Decimal Value 0 227 228 Table 1. Example Volume Settings CS4220 CS4221 2 1 ATT2 ATT1 0 0 Volume Setting 0 dB -113.5 dB Muted 0 ATT0 0 15 ...
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... Right justified, 24-bit 11- Right justified, 20-bit Function: The required relationship between the left/right clock, serial clock and input serial data is defined by the Serial Data Input Format, and the options are detailed in Figures 8-11 DEM0 DSCK DOF1 CS4220 CS4221 DOF0 DIF1 DIF0 DS284PP3 ...
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... XTI = 512 Fs for Master Mode Function: The MCK bits allow for control of the Master Clock, XTI, input frequency. Note: These bits are not valid when operating in slave mode. DS284PP3 LVR2 LVR1 LVR0 Reserved Reserved CS4220 CS4221 LVL2 LVL2 LVL0 Reserved MCK1 MCK0 ...
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... SDIN SDIN AINL+ AINL+ DIF1 DIF1 AINL- AINL- DIF0 DIF0 DEM1 DEM1 DEM0 DEM0 AINR+ AINR AINR- AINR (kHz) XTI (MHz) 256x 32 8.1920 44.1 11.2896 48 12.2880 Table 2. Common Clock Frequencies CS4220 CS4221 384x 512x 12.2880 16.3840 16.9344 22.5792 18.4320 24.5760 DS284PP3 ...
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... DESCRIPTION 24-bit data 0 1 Left Justified 24-bit data 1 0 Right Justified, 24-bit Data 1 1 Right Justified, 20-bit Data Table 3. Digital Interface Format - DIF1 and DIF0 DEM1 De-Emphasis kHz 0 1 44.1 kHz kHz 1 1 Disabled Table 4. De-emphasis Control CS4220 CS4221 FORMAT FIGURE ...
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... Crystal Connections ( Input/Output ) - Input and output connections for the crystal used to clock the CS4221. Alternatively a clock may be input into XTI. This is the clock source for the delta-sigma modulator and digital filters. The frequency of this clock must be either 256x, 384x, or 512x Fs. The default XTI setting in Master Mode is 256x, but this may be changed to 384x or 512x through the Control Port ...
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... DSP Port Mode (05h) register. The options are detailed in Figures 8 - 11. SCL/CCLK 10 Serial Control Port Clock ( Input ) - Clocks the serial control bits into and out of the CS4221 SDA/CDIN 11 ...
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... De-emphasis control is achieved with the DEM1/0 pins on the CS4220 or through the DEM1-0 bits in the DSP Port Mode Byte (#5) on the CS4221. 8.7 Power-up / Reset / Power Down Calibration Upon power up, the user should hold RST = 0 for approximately 10 ms ...
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... INCR bit in the MAP register. If INCR is a zero, then the MAP will stay constant for successive writes. If INCR is set then MAP will auto increment after each byte is written, al- lowing block writes of successive registers. Regis- ter reading from the CS4221 is not supported in the SPI mode. 2 8.8.2 I ...
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... CHIP ADDRESS MAP 0010000 R/W MAP = Memory Address Pointer Figure 6. Control Port Timing, SPI mode ADDR R/W ACK DATA 1-8 AD0 Figure 7. Control Port Timing, I CS4220 CS4221 2 1 MAP2 MAP1 0 0 DATA MSB LSB byte 1 byte n ACK DATA 1-8 ACK ...
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... XTI = 256, 384, 512 Fs LRCK = kHz SCLK = 48, 64, 128 Fs Figure 9. Serial Audio Format Right-justified, 24-bit data XTI = 256, 384, 512 Fs LRCK = kHz SCLK = 64 Fs Figure 10. Serial Audio Format 2 CS4220 CS4221 Right Channel + LSB Slave 2 S) Right Channel + LSB Slave Right Channel ...
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... SCLK = 64 Fs Input Right-justified, 20-bit data XTI = 256, 384, 512 Fs LRCK = kHz SCLK = 64 Fs Figure 11. Serial Audio Format 3 Figure 12. Optional Input Buffer 150 + AINR+ 2 µF AINR- 4.7 µF + 0.1 µF Figure 13. Single-ended Input Application CS4220 CS4221 Right Channel Slave CS4223 DS284PP3 ...
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... Gain µ - Figure 15. De-emphasis Curve DS284PP3 Figure 14. 2- and 3-Pole Butterworth Filters µs F2 Frequency Figure 16. Hybrid Analog/Digital Attenuation CS4220 CS4221 Analog Digital 0 Signal Noise 0 -113.5 Attenuation (dB) 27 ...
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... ADC/DAC FILTER RESPONSE Figure 17. ADC Filter Response Figure 19. ADC Transition Band Figure 21. DAC Passband Ripple 28 CS4220 CS4221 Figure 18. ADC Passband Ripple Figure 20. DAC Filter Response Figure 22. DAC Transition Band DS284PP3 ...
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... The change in gain value with temperature. Units in ppm/°C. Offset Error For the ADCs, the deviation in LSB's of the output from mid-scale with the selected inputs tied to a com- mon potential. For the DAC's, the differential output voltage with mid-scale input code. Units are in volts. DS284PP3 CS4220 CS4221 29 ...
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... JEDEC #: MO-150 Controlling Dimension is Millimeters CS4220 CS4221 END VIEW L PLANE MILLIMETERS NOM MAX -- -- 2.13 0.15 0.25 1.75 1.88 -- 0.38 10.20 10.50 7.80 8 ...
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Notes • ...
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