SL23EP05SI-1 Silicon Laboratories Inc, SL23EP05SI-1 Datasheet - Page 9

• Manufacturer Part Number: SL23EP05SI-1
• Description: Clock Buffer 10-220MHz 5 Outputs ZDB 3.3-2.5V
• Manufacturer: Silicon Laboratories Inc

Specifications of SL23EP05SI-1

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

External Components & Design Considerations
Typical Application Schematic
Comments and Recommendations
Decoupling Capacitor: A minimum decoupling capacitor of 0.1μF must be used between VDD and VSS on the pins 6 and 4.
Additional capacitors may be necessary depending on the application. Place the capacitor on the component side of the PCB
as close to the VDD pin as possible. The PCB trace to the VDD pin and to the GND via should be kept as short as possible.
Do not use vias between the decoupling capacitor and the VDD pin.
Series Termination Resistor: A series termination resistor is recommended if the distance between the output (SSCLK) and
the load is over 1 ½ inch. The nominal impedance of the SSCLK output is about 30 Ω. Use 20 Ω resistor in series with the
output to terminate 50Ω trace impedance and place 20 Ω resistor as close to the clock outputs as possible.
Zero Delay and Skew Control: All outputs and CLKIN pins should be loaded with the same load to achieve “Zero Delay”
between the CLKIN and the outputs. The CLKOUT pin is connected to CLKIN internally on-chip for internal feedback to PLL,
and sees an additional 2 pF load with respect to the clock pins. For applications requiring zero input/output delay, the load at
the all output pins including the CLKOUT pin must be the same. If any delay adjustment is required, the capacitance at the
CLKOUT pin could be increased or decreased to increase or decrease the delay between clocks and CLKIN.
Rev 2.2, June 30, 2009
For minimum pin-to-pin skew, the external load at the clocks must be the same.
CLKIN
VDD
0.1μF
1
6
SL23EP05
GND
4
8
3
7
CL
CL
CL
CLKOUT
CLK1
CLK4
SL23EP05
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