CY28409OC Silicon Laboratories Inc, CY28409OC Datasheet - Page 8

• Manufacturer Part Number: CY28409OC
• Description: Clock Synthesizer / Jitter Cleaner SysClk Intel Grntsdl 865 and 875 chipsets
• Manufacturer: Silicon Laboratories Inc

Specifications of CY28409OC

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Rev 1.0, November 22, 2006
Calculating Load Capacitors
In addition to the standard external trim capacitors, trace
capacitance and pin capacitance must also be considered to
correctly calculate crystal loading. As mentioned previously,
the capacitance on each side of the crystal is in series with the
crystal. This means the total capacitance on each side of the
crystal must be twice the specified crystal load capacitance
(CL). While the capacitance on each side of the crystal is in
series with the crystal, trim capacitors (Ce1,Ce2) should be
calculated to provide equal capacitive loading on both sides.
C s 1
Figure 2. Crystal Loading Example
C e 1
CPUC, 133MHz
CPUT, 133MHz
SRCC 100MHz
SRCT 100MHz
X 1
3V66, 66MHz
C i1
USB, 48MHz
PCI, 33MHz
C lo c k C h ip
( C Y 2 8 4 0 9 )
X T A L
REF
PD#
C i2
X 2
C e 2
Figure 3. Power-down Assertion Timing Waveform
C s 2
3 t o 6 p
3 3 p F
P in
T r im
2 . 8 p F
T r a c e
Use the following formulas to calculate the trim capacitor
values for Ce1 and Ce2.
CL....................................................Crystal load capacitance
CLe......................................... Actual loading seen by crystal
using standard value trim capacitors
Ce..................................................... External trim capacitors
Cs .............................................. Stray capacitance (terraced)
Ci ...........................................................Internal capacitance
(lead frame, bond wires etc.)
PD# (Power-down) Clarification
The PD# (Power-down) pin is used to shut off ALL clocks prior
to shutting off power to the device. PD# is an asynchronous
active LOW input. This signal is synchronized internally to the
device powering down the clock synthesizer. PD# is an
asynchronous function for powering up the system. When PD#
is LOW, all clocks are driven to a LOW value and held there
and the VCO and PLLs are also powered down. All clocks are
shut down in a synchronous manner so as not to cause
glitches while changing to the low ‘stopped’ state.
PD# Assertion
When PD# is sampled LOW by two consecutive rising edges
of the CPUC clock then all clock outputs (except CPU) clocks
must be held LOW on their next HIGH-to-LOW transition. CPU
clocks must be held with CPU clock pin driven HIGH with a
value of 2 x Iref and CPUC undriven. Due to the state of
internal logic, stopping and holding the REF clock outputs in
the LOW state may require more than one clock cycle to
complete
CLe
Total Capacitance (as seen by the crystal)
=
(
Load Capacitance (each side)
Ce1 + Cs1 + Ci1
Ce = 2 * CL – (Cs + Ci)
1
+
1
Ce2 + Cs2 + Ci2
1
CY28409
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